Loading arch/mips/Kconfig +1 −14 Original line number Diff line number Diff line Loading @@ -132,7 +132,6 @@ config BCM63XX select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 select NR_CPUS_DEFAULT_2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_HAS_EARLY_PRINTK Loading Loading @@ -612,7 +611,6 @@ config SIBYTE_SWARM select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 Loading @@ -626,7 +624,6 @@ config SIBYTE_LITTLESUR select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 Loading @@ -638,7 +635,6 @@ config SIBYTE_SENTOSA bool "Sibyte BCM91250E-Sentosa" select BOOT_ELF32 select DMA_COHERENT select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 Loading Loading @@ -1866,7 +1862,6 @@ config MIPS_MT_SMP select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT select NR_CPUS_DEFAULT_2 select SMP select SYS_SUPPORTS_SCHED_SMT if SMP select SYS_SUPPORTS_SMP Loading Loading @@ -2177,12 +2172,6 @@ config SYS_SUPPORTS_MIPS_CMP config SYS_SUPPORTS_SMP bool config NR_CPUS_DEFAULT_1 bool config NR_CPUS_DEFAULT_2 bool config NR_CPUS_DEFAULT_4 bool Loading @@ -2200,10 +2189,8 @@ config NR_CPUS_DEFAULT_64 config NR_CPUS int "Maximum number of CPUs (2-64)" range 1 64 if NR_CPUS_DEFAULT_1 range 2 64 depends on SMP default "1" if NR_CPUS_DEFAULT_1 default "2" if NR_CPUS_DEFAULT_2 default "4" if NR_CPUS_DEFAULT_4 default "8" if NR_CPUS_DEFAULT_8 default "16" if NR_CPUS_DEFAULT_16 Loading arch/mips/kernel/mcount.S +1 −1 Original line number Diff line number Diff line Loading @@ -83,7 +83,7 @@ _mcount: PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) #endif move a0, ra /* arg1: self return address */ PTR_SUBU a0, ra, 8 /* arg1: self address */ .globl ftrace_call ftrace_call: nop /* a placeholder for the call to a real tracing function */ Loading arch/mips/kernel/time.c +9 −1 Original line number Diff line number Diff line Loading @@ -121,6 +121,14 @@ void __init time_init(void) { plat_time_init(); if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) /* * The use of the R4k timer as a clock event takes precedence; * if reading the Count register might interfere with the timer * interrupt, then we don't use the timer as a clock source. * We may still use the timer as a clock source though if the * timer interrupt isn't reliable; the interference doesn't * matter then, because we don't use the interrupt. */ if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug()) init_mips_clocksource(); } arch/mips/loongson/common/Makefile +2 −1 Original line number Diff line number Diff line Loading @@ -3,8 +3,9 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ pci.o bonito-irq.o mem.o machtype.o platform.o bonito-irq.o mem.o machtype.o platform.o obj-$(CONFIG_GPIOLIB) += gpio.o obj-$(CONFIG_PCI) += pci.o # # Serial port support Loading arch/mips/mm/gup.c +2 −1 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ #include <linux/swap.h> #include <linux/hugetlb.h> #include <asm/cpu-features.h> #include <asm/pgtable.h> static inline pte_t gup_get_pte(pte_t *ptep) Loading Loading @@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, len = (unsigned long) nr_pages << PAGE_SHIFT; end = start + len; if (end < start) if (end < start || cpu_has_dc_aliases) goto slow_irqon; /* XXX: batch / limit 'nr' */ Loading Loading
arch/mips/Kconfig +1 −14 Original line number Diff line number Diff line Loading @@ -132,7 +132,6 @@ config BCM63XX select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 select NR_CPUS_DEFAULT_2 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_HAS_EARLY_PRINTK Loading Loading @@ -612,7 +611,6 @@ config SIBYTE_SWARM select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 Loading @@ -626,7 +624,6 @@ config SIBYTE_LITTLESUR select BOOT_ELF32 select DMA_COHERENT select HAVE_PATA_PLATFORM select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 Loading @@ -638,7 +635,6 @@ config SIBYTE_SENTOSA bool "Sibyte BCM91250E-Sentosa" select BOOT_ELF32 select DMA_COHERENT select NR_CPUS_DEFAULT_2 select SIBYTE_SB1250 select SWAP_IO_SPACE select SYS_HAS_CPU_SB1 Loading Loading @@ -1866,7 +1862,6 @@ config MIPS_MT_SMP select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_IRQ_EI select MIPS_MT select NR_CPUS_DEFAULT_2 select SMP select SYS_SUPPORTS_SCHED_SMT if SMP select SYS_SUPPORTS_SMP Loading Loading @@ -2177,12 +2172,6 @@ config SYS_SUPPORTS_MIPS_CMP config SYS_SUPPORTS_SMP bool config NR_CPUS_DEFAULT_1 bool config NR_CPUS_DEFAULT_2 bool config NR_CPUS_DEFAULT_4 bool Loading @@ -2200,10 +2189,8 @@ config NR_CPUS_DEFAULT_64 config NR_CPUS int "Maximum number of CPUs (2-64)" range 1 64 if NR_CPUS_DEFAULT_1 range 2 64 depends on SMP default "1" if NR_CPUS_DEFAULT_1 default "2" if NR_CPUS_DEFAULT_2 default "4" if NR_CPUS_DEFAULT_4 default "8" if NR_CPUS_DEFAULT_8 default "16" if NR_CPUS_DEFAULT_16 Loading
arch/mips/kernel/mcount.S +1 −1 Original line number Diff line number Diff line Loading @@ -83,7 +83,7 @@ _mcount: PTR_S MCOUNT_RA_ADDRESS_REG, PT_R12(sp) #endif move a0, ra /* arg1: self return address */ PTR_SUBU a0, ra, 8 /* arg1: self address */ .globl ftrace_call ftrace_call: nop /* a placeholder for the call to a real tracing function */ Loading
arch/mips/kernel/time.c +9 −1 Original line number Diff line number Diff line Loading @@ -121,6 +121,14 @@ void __init time_init(void) { plat_time_init(); if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) /* * The use of the R4k timer as a clock event takes precedence; * if reading the Count register might interfere with the timer * interrupt, then we don't use the timer as a clock source. * We may still use the timer as a clock source though if the * timer interrupt isn't reliable; the interference doesn't * matter then, because we don't use the interrupt. */ if (mips_clockevent_init() != 0 || !cpu_has_mfc0_count_bug()) init_mips_clocksource(); }
arch/mips/loongson/common/Makefile +2 −1 Original line number Diff line number Diff line Loading @@ -3,8 +3,9 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ pci.o bonito-irq.o mem.o machtype.o platform.o bonito-irq.o mem.o machtype.o platform.o obj-$(CONFIG_GPIOLIB) += gpio.o obj-$(CONFIG_PCI) += pci.o # # Serial port support Loading
arch/mips/mm/gup.c +2 −1 Original line number Diff line number Diff line Loading @@ -12,6 +12,7 @@ #include <linux/swap.h> #include <linux/hugetlb.h> #include <asm/cpu-features.h> #include <asm/pgtable.h> static inline pte_t gup_get_pte(pte_t *ptep) Loading Loading @@ -273,7 +274,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write, len = (unsigned long) nr_pages << PAGE_SHIFT; end = start + len; if (end < start) if (end < start || cpu_has_dc_aliases) goto slow_irqon; /* XXX: batch / limit 'nr' */ Loading