Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4ca2ad55 authored by Fugang Duan's avatar Fugang Duan Committed by Shawn Guo
Browse files

ARM: imx6sl: add missing enet clock for imx6sl



There's a enet clock gate missing in clock tree, thus add it.

Signed-off-by: default avatarFugang Duan <B38611@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@freescale.com>
parent 7171511e
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -312,6 +312,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
	clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
	clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
	clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
	clks[IMX6SL_CLK_ENET]         = imx_clk_gate2("enet",         "ipg",               base + 0x6c, 10);
	clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
	clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
	clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
+2 −1
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@
#define IMX6SL_CLK_USDHC4		132
#define IMX6SL_CLK_PLL4_AUDIO_DIV	133
#define IMX6SL_CLK_SPBA			134
#define IMX6SL_CLK_END			135
#define IMX6SL_CLK_ENET			135
#define IMX6SL_CLK_END			136

#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */