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Commit 4c9f2422 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-iproc' into clk-next 

* clk-iproc:
  clk: iproc: Remove __init from header
  clk: iproc: Add support for Cygnus audio clocks
  Documentation: dt-bindings: Add DT bindings for Cygnus audio clock
parents b9e65ebc df416e56

Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt

+6 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ PLL and leaf clock compatible strings for Cygnus are: 
    "brcm,cygnus-lcpll0"

    "brcm,cygnus-mipipll"

    "brcm,cygnus-asiu-clk"

    "brcm,cygnus-audiopll"



The following table defines the set of PLL/clock index and ID for Cygnus.

These clock IDs are defined in:
@@ -131,6 +132,11 @@ These clock IDs are defined in: 
    ch4_unused mipipll          5       BCM_CYGNUS_MIPIPLL_CH4_UNUSED

    ch5_unused mipipll          6       BCM_CYGNUS_MIPIPLL_CH5_UNUSED



    audiopll   crystal          0       BCM_CYGNUS_AUDIOPLL

    ch0_audio  audiopll         1       BCM_CYGNUS_AUDIOPLL_CH0

    ch1_audio  audiopll         2       BCM_CYGNUS_AUDIOPLL_CH1

    ch2_audio  audiopll         3       BCM_CYGNUS_AUDIOPLL_CH2



Northstar and Northstar Plus

------

PLL and leaf clock compatible strings for Northstar and Northstar Plus are:

drivers/clk/bcm/clk-cygnus.c

+59 −0
Original line number Diff line number Diff line
@@ -268,3 +268,62 @@ static void __init cygnus_asiu_init(struct device_node *node) 
	iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div));

}

CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);



/*

 * AUDIO PLL VCO frequency parameter table

 *

 * PLL output frequency = ((ndiv_int + ndiv_frac / 2^20) *

 * (parent clock rate / pdiv)

 *

 * On Cygnus, parent is the 25MHz oscillator

 */

static const struct iproc_pll_vco_param audiopll_vco_params[] = {

	/* rate (Hz) ndiv_int ndiv_frac pdiv */

	{ 1354750204UL,  54,     199238,   1 },

	{ 1769470191UL,  70,     816639,   1 },

};



static const struct iproc_pll_ctrl audiopll = {

	.flags = IPROC_CLK_PLL_NEEDS_SW_CFG | IPROC_CLK_PLL_HAS_NDIV_FRAC |

		IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW,

	.reset = RESET_VAL(0x5c, 0, 1),

	.dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3),

	.sw_ctrl = SW_CTRL_VAL(0x4, 0),

	.ndiv_int = REG_VAL(0x8, 0, 10),

	.ndiv_frac = REG_VAL(0x8, 10, 20),

	.pdiv = REG_VAL(0x44, 0, 4),

	.vco_ctrl = VCO_CTRL_VAL(0x0c, 0x10),

	.status = REG_VAL(0x54, 0, 1),

	.macro_mode = REG_VAL(0x0, 0, 3),

};



static const struct iproc_clk_ctrl audiopll_clk[] = {

	[BCM_CYGNUS_AUDIOPLL_CH0] = {

		.channel = BCM_CYGNUS_AUDIOPLL_CH0,

		.flags = IPROC_CLK_AON |

				IPROC_CLK_MCLK_DIV_BY_2,

		.enable = ENABLE_VAL(0x14, 8, 10, 9),

		.mdiv = REG_VAL(0x14, 0, 8),

	},

	[BCM_CYGNUS_AUDIOPLL_CH1] = {

		.channel = BCM_CYGNUS_AUDIOPLL_CH1,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x18, 8, 10, 9),

		.mdiv = REG_VAL(0x18, 0, 8),

	},

	[BCM_CYGNUS_AUDIOPLL_CH2] = {

		.channel = BCM_CYGNUS_AUDIOPLL_CH2,

		.flags = IPROC_CLK_AON,

		.enable = ENABLE_VAL(0x1c, 8, 10, 9),

		.mdiv = REG_VAL(0x1c, 0, 8),

	},

};



static void __init cygnus_audiopll_clk_init(struct device_node *node)

{

	iproc_pll_clk_setup(node, &audiopll, audiopll_vco_params,

			    ARRAY_SIZE(audiopll_vco_params), audiopll_clk,

			    ARRAY_SIZE(audiopll_clk));

}

CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",

			cygnus_audiopll_clk_init);

drivers/clk/bcm/clk-iproc-pll.c

+36 −5
Original line number Diff line number Diff line
@@ -25,6 +25,12 @@ 
#define PLL_VCO_HIGH_SHIFT 19

#define PLL_VCO_LOW_SHIFT  30



/*

 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies

 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers

 */

#define PLL_USER_MODE 7



/* number of delay loops waiting for PLL to lock */

#define LOCK_DELAY 100
@@ -215,7 +221,10 @@ static void __pll_put_in_reset(struct iproc_pll *pll) 
	const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;



	val = readl(pll->control_base + reset->offset);

	val &= ~(1 << reset->reset_shift | 1 << reset->p_reset_shift);

	if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW)

		val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift);

	else

		val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift));

	iproc_pll_write(pll, pll->control_base, reset->offset, val);

}
@@ -236,7 +245,10 @@ static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, 
	iproc_pll_write(pll, pll->control_base, dig_filter->offset, val);



	val = readl(pll->control_base + reset->offset);

	val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;

	if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW)

		val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift));

	else

		val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift);

	iproc_pll_write(pll, pll->control_base, reset->offset, val);

}
@@ -292,6 +304,16 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, 
	/* put PLL in reset */

	__pll_put_in_reset(pll);



	/* set PLL in user mode before modifying PLL controls */

	if (ctrl->flags & IPROC_CLK_PLL_USER_MODE_ON) {

		val = readl(pll->control_base + ctrl->macro_mode.offset);

		val &= ~(bit_mask(ctrl->macro_mode.width) <<

			ctrl->macro_mode.shift);

		val |= PLL_USER_MODE << ctrl->macro_mode.shift;

		iproc_pll_write(pll, pll->control_base,

			ctrl->macro_mode.offset, val);

	}



	iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0);



	val = readl(pll->control_base + ctrl->vco_ctrl.l_offset);
@@ -505,6 +527,9 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, 
	if (mdiv == 0)

		mdiv = 256;



	if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)

		clk->rate = parent_rate / (mdiv * 2);

	else

		clk->rate = parent_rate / mdiv;



	return clk->rate;
@@ -543,6 +568,9 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (rate == 0 || parent_rate == 0)

		return -EINVAL;



	if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)

		div = DIV_ROUND_UP(parent_rate, rate * 2);

	else

		div = DIV_ROUND_UP(parent_rate, rate);

	if (div > 256)

		return -EINVAL;
@@ -555,6 +583,9 @@ static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, 
		val |= div << ctrl->mdiv.shift;

	}

	iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val);

	if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2)

		clk->rate = parent_rate / (div * 2);

	else

		clk->rate = parent_rate / div;



	return 0;

drivers/clk/bcm/clk-iproc.h

+32 −11
Original line number Diff line number Diff line
@@ -60,6 +60,26 @@ 
 */

#define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)



/*

 * Some PLLs have an additional divide by 2 in master clock calculation;

 * MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know

 * of modified calculations

 */

#define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)



/*

 * Some PLLs provide a look up table for the leaf clock frequencies and

 * auto calculates VCO frequency parameters based on the provided leaf

 * clock frequencies. They have a user mode that allows the divider

 * controls to be determined by the user

 */

#define IPROC_CLK_PLL_USER_MODE_ON BIT(8)



/*

 * Some PLLs have an active low reset

 */

#define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)



/*

 * Parameters for VCO frequency configuration

 *
@@ -149,6 +169,7 @@ struct iproc_pll_ctrl { 
	struct iproc_clk_reg_op pdiv;

	struct iproc_pll_vco_ctrl vco_ctrl;

	struct iproc_clk_reg_op status;

	struct iproc_clk_reg_op macro_mode;

};



/*
@@ -183,14 +204,14 @@ struct iproc_asiu_div { 
	unsigned int low_width;

};



void __init iproc_armpll_setup(struct device_node *node);

void __init iproc_pll_clk_setup(struct device_node *node,

void iproc_armpll_setup(struct device_node *node);

void iproc_pll_clk_setup(struct device_node *node,

			 const struct iproc_pll_ctrl *pll_ctrl,

			 const struct iproc_pll_vco_param *vco,

			 unsigned int num_vco_entries,

			 const struct iproc_clk_ctrl *clk_ctrl,

			 unsigned int num_clks);

void __init iproc_asiu_setup(struct device_node *node,

void iproc_asiu_setup(struct device_node *node,

		      const struct iproc_asiu_div *div,

		      const struct iproc_asiu_gate *gate,

		      unsigned int num_clks);

include/dt-bindings/clock/bcm-cygnus.h

+6 −0
Original line number Diff line number Diff line
@@ -65,4 +65,10 @@ 
#define BCM_CYGNUS_ASIU_ADC_CLK       1

#define BCM_CYGNUS_ASIU_PWM_CLK       2



/* AUDIO clock ID */

#define BCM_CYGNUS_AUDIOPLL           0

#define BCM_CYGNUS_AUDIOPLL_CH0       1

#define BCM_CYGNUS_AUDIOPLL_CH1       2

#define BCM_CYGNUS_AUDIOPLL_CH2       3



#endif /* _CLOCK_BCM_CYGNUS_H */