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Commit 4c4b22ab authored by Zhao Yan's avatar Zhao Yan Committed by Zhenyu Wang
Browse files

drm/i915/gvt: add more registers to context save/restore list 



the value of those registers should be applied to hardware on
context restoring

Signed-off-by: default avatarZhao Yan <yan.y.zhao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent d8e9b2b9

drivers/gpu/drm/i915/gvt/render.c

+16 −0
Original line number Diff line number Diff line
@@ -53,6 +53,14 @@ static struct render_mmio gen8_render_mmio_list[] = { 
	{RCS, _MMIO(0x24d4), 0, false},

	{RCS, _MMIO(0x24d8), 0, false},

	{RCS, _MMIO(0x24dc), 0, false},

	{RCS, _MMIO(0x24e0), 0, false},

	{RCS, _MMIO(0x24e4), 0, false},

	{RCS, _MMIO(0x24e8), 0, false},

	{RCS, _MMIO(0x24ec), 0, false},

	{RCS, _MMIO(0x24f0), 0, false},

	{RCS, _MMIO(0x24f4), 0, false},

	{RCS, _MMIO(0x24f8), 0, false},

	{RCS, _MMIO(0x24fc), 0, false},

	{RCS, _MMIO(0x7004), 0xffff, true},

	{RCS, _MMIO(0x7008), 0xffff, true},

	{RCS, _MMIO(0x7000), 0xffff, true},
@@ -76,6 +84,14 @@ static struct render_mmio gen9_render_mmio_list[] = { 
	{RCS, _MMIO(0x24d4), 0, false},

	{RCS, _MMIO(0x24d8), 0, false},

	{RCS, _MMIO(0x24dc), 0, false},

	{RCS, _MMIO(0x24e0), 0, false},

	{RCS, _MMIO(0x24e4), 0, false},

	{RCS, _MMIO(0x24e8), 0, false},

	{RCS, _MMIO(0x24ec), 0, false},

	{RCS, _MMIO(0x24f0), 0, false},

	{RCS, _MMIO(0x24f4), 0, false},

	{RCS, _MMIO(0x24f8), 0, false},

	{RCS, _MMIO(0x24fc), 0, false},

	{RCS, _MMIO(0x7004), 0xffff, true},

	{RCS, _MMIO(0x7008), 0xffff, true},

	{RCS, _MMIO(0x7000), 0xffff, true},