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Commit 4c45852f authored by Gabriele Paoloni's avatar Gabriele Paoloni Committed by Bjorn Helgaas
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PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces 



Callers of dw_pcie_cfg_read() and dw_pcie_cfg_write() previously had to
split the address into "addr" and "where".  The callees assumed "addr" was
32-bit aligned (with zeros in the low two bits) and they used only the low
two bits of "where".

Accept the entire address in "addr" and drop the now-redundant "where"
argument.  As an example, this replaces this:

  int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
    *val = readb(addr + (where & 1));

with this:

  int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
    *val = readb(addr):

[bhelgaas: changelog, split access size change to separate patch]
Signed-off-by: default avatarGabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent c003ca99

drivers/pci/host/pci-exynos.c

+2 −3
Original line number Diff line number Diff line
@@ -454,7 +454,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 
	int ret;



	exynos_pcie_sideband_dbi_r_mode(pp, true);

	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);

	ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);

	exynos_pcie_sideband_dbi_r_mode(pp, false);

	return ret;

}
@@ -465,8 +465,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 
	int ret;



	exynos_pcie_sideband_dbi_w_mode(pp, true);

	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),

			where, size, val);

	ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);

	exynos_pcie_sideband_dbi_w_mode(pp, false);

	return ret;

}

drivers/pci/host/pci-keystone-dw.c

+2 −2
Original line number Diff line number Diff line
@@ -398,7 +398,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 


	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);



	return dw_pcie_cfg_read(addr + (where & ~0x3), where, size, val);

	return dw_pcie_cfg_read(addr + where, size, val);

}



int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -410,7 +410,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 


	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);



	return dw_pcie_cfg_write(addr + (where & ~0x3), where, size, val);

	return dw_pcie_cfg_write(addr + where, size, val);

}



/**

drivers/pci/host/pcie-designware.c

+12 −16
Original line number Diff line number Diff line
@@ -80,14 +80,14 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys) 
	return sys->private_data;

}



int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)

int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)

{

	if (size == 4)

		*val = readl(addr);

	else if (size == 2)

		*val = readw(addr + (where & 2));

		*val = readw(addr);

	else if (size == 1)

		*val = readb(addr + (where & 1));

		*val = readb(addr);

	else {

		*val = 0;

		return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -96,14 +96,14 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val) 
	return PCIBIOS_SUCCESSFUL;

}



int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)

int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)

{

	if (size == 4)

		writel(val, addr);

	else if (size == 2)

		writew(val, addr + (where & 2));

		writew(val, addr);

	else if (size == 1)

		writeb(val, addr + (where & 3));

		writeb(val, addr);

	else

		return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -134,8 +134,7 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 
	if (pp->ops->rd_own_conf)

		ret = pp->ops->rd_own_conf(pp, where, size, val);

	else

		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,

				size, val);

		ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);



	return ret;

}
@@ -148,8 +147,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 
	if (pp->ops->wr_own_conf)

		ret = pp->ops->wr_own_conf(pp, where, size, val);

	else

		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,

				size, val);

		ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);



	return ret;

}
@@ -585,13 +583,12 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
		u32 devfn, int where, int size, u32 *val)

{

	int ret, type;

	u32 address, busdev, cfg_size;

	u32 busdev, cfg_size;

	u64 cpu_addr;

	void __iomem *va_cfg_base;



	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |

		 PCIE_ATU_FUNC(PCI_FUNC(devfn));

	address = where & ~0x3;



	if (bus->parent->number == pp->root_bus_nr) {

		type = PCIE_ATU_TYPE_CFG0;
@@ -608,7 +605,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,

				  type, cpu_addr,

				  busdev, cfg_size);

	ret = dw_pcie_cfg_read(va_cfg_base + address, where, size, val);

	ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);

	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,

				  PCIE_ATU_TYPE_IO, pp->io_mod_base,

				  pp->io_bus_addr, pp->io_size);
@@ -620,13 +617,12 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
		u32 devfn, int where, int size, u32 val)

{

	int ret, type;

	u32 address, busdev, cfg_size;

	u32 busdev, cfg_size;

	u64 cpu_addr;

	void __iomem *va_cfg_base;



	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |

		 PCIE_ATU_FUNC(PCI_FUNC(devfn));

	address = where & ~0x3;



	if (bus->parent->number == pp->root_bus_nr) {

		type = PCIE_ATU_TYPE_CFG0;
@@ -643,7 +639,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,

				  type, cpu_addr,

				  busdev, cfg_size);

	ret = dw_pcie_cfg_write(va_cfg_base + address, where, size, val);

	ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);

	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,

				  PCIE_ATU_TYPE_IO, pp->io_mod_base,

				  pp->io_bus_addr, pp->io_size);

drivers/pci/host/pcie-designware.h

+2 −2
Original line number Diff line number Diff line
@@ -76,8 +76,8 @@ struct pcie_host_ops { 
	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);

};



int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);

int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);

int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);

int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);

irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);

void dw_pcie_msi_init(struct pcie_port *pp);

int dw_pcie_link_up(struct pcie_port *pp);

drivers/pci/host/pcie-spear13xx.c

+8 −10
Original line number Diff line number Diff line
@@ -163,14 +163,12 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) 
	 * default value in capability register is 512 bytes. So force

	 * it to 128 here.

	 */

	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL,

				0, 2, &val);

	dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);

	val &= ~PCI_EXP_DEVCTL_READRQ;

	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL,

				0, 2, val);

	dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);



	dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 0, 2, 0x104A);

	dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 2, 0xCD80);

	dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A);

	dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);



	/*

	 * if is_gen1 is set then handle it, so that some buggy card
@@ -178,21 +176,21 @@ static int spear13xx_pcie_establish_link(struct pcie_port *pp) 
	 */

	if (spear13xx_pcie->is_gen1) {

		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,

					0, 4, &val);

					4, &val);

		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			val &= ~((u32)PCI_EXP_LNKCAP_SLS);

			val |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +

						PCI_EXP_LNKCAP, 0, 4, val);

				PCI_EXP_LNKCAP, 4, val);

		}



		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,

					0, 2, &val);

					2, &val);

		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			val &= ~((u32)PCI_EXP_LNKCAP_SLS);

			val |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +

						PCI_EXP_LNKCTL2, 0, 2, val);

					PCI_EXP_LNKCTL2, 2, val);

		}

	}