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Commit 4c287151 authored by Mao Jinlong's avatar Mao Jinlong
Browse files

ARM: dts: msm: Add npu tpdms and dcc tpdm for Kona 



Add npu tpdms and dcc tpdm for Kona to support hardware events
collection of npu and dcc list via atb of DCC.

Change-Id: Ib80adbac47ea2a61eaed93bd951444c354269767
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent a5d36bfa

arch/arm64/boot/dts/qcom/kona-coresight.dtsi

+368 −70
Original line number Diff line number Diff line
@@ -19,7 +19,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				replicator0_out_tmc_etr: endpoint {
@@ -116,7 +115,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				tmc_etf_swao_out_replicator_swao: endpoint {
@@ -151,7 +149,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_swao_out_tmc_etf_swao: endpoint {
@@ -216,7 +213,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				tpda_swao_out_funnel_swao: endpoint {
@@ -335,7 +331,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_merg_out_funnel_swao: endpoint {
@@ -427,7 +422,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_in0_out_funnel_merg: endpoint {
@@ -470,7 +464,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_in1_out_funnel_merg: endpoint {
@@ -527,13 +520,12 @@ 
				     <25 32>;

		qcom,cmb-elem-size = <7 64>,

				     <13 64>,

				     <15 64>,

				     <15 32>,

				     <16 64>,

				     <17 64>,

				     <18 64>,

				     <20 64>,

				     <21 64>,

				     <22 64>,

				     <23 64>,

				     <25 64>;
@@ -578,7 +570,7 @@ 
				};

			};



			port@5 {

			port@4 {

				reg = <10>;

				tpda_10_in_funnel_dl_center: endpoint {

					slave-mode;
@@ -587,7 +579,7 @@ 
				};

			};



			port@6 {

			port@5 {

				reg = <11>;

				tpda_11_in_tpdm_ddr_ch02: endpoint {

					slave-mode;
@@ -596,7 +588,7 @@ 
				};

			};



			port@7 {

			port@6 {

				reg = <12>;

				tpda_12_in_tpdm_ddr_ch13: endpoint {

					slave-mode;
@@ -605,7 +597,7 @@ 
				};

			};



			port@8 {

			port@7 {

				reg = <13>;

				tpda_13_in_tpdm_ddr: endpoint {

					slave-mode;
@@ -614,7 +606,7 @@ 
				};

			};



			port@9 {

			port@8 {

				reg = <14>;

				tpda_14_in_tpdm_turing: endpoint {

					slave-mode;
@@ -623,7 +615,7 @@ 
				};

			};



			port@10 {

			port@9 {

				reg = <15>;

				tpda_15_in_tpdm_llm_turing: endpoint {

					slave-mode;
@@ -632,7 +624,34 @@ 
				};

			};



			port@10 {

				reg = <16>;

				tpda_16_in_tpdm_npu: endpoint {

					slave-mode;

					remote-endpoint =

						<&tpdm_npu_out_tpda16>;

				};

			};



			port@11 {

				reg = <17>;

				tpda_17_in_tpdm_npu_llm: endpoint {

					slave-mode;

					remote-endpoint =

						<&tpdm_npu_llm_out_tpda17>;

				};

			};



			port@12 {

				reg = <18>;

				tpda_18_in_tpdm_npu_dpm: endpoint {

					slave-mode;

					remote-endpoint =

						<&tpdm_npu_dpm_out_tpda18>;

				};

			};



			port@13 {

				reg = <19>;

				tpda_19_in_tpdm_dlct: endpoint {

					slave-mode;
@@ -641,7 +660,7 @@ 
				};

			};



			port@12 {

			port@14 {

				reg = <20>;

				tpda_20_in_tpdm_ipcc: endpoint {

					slave-mode;
@@ -650,7 +669,7 @@ 
				};

			};



			port@13 {

			port@15 {

				reg = <21>;

				tpda_in_tpdm_vsense: endpoint {

					slave-mode;
@@ -659,7 +678,16 @@ 
				};

			};



			port@14 {

			port@16 {

				reg = <22>;

				tpda_in_tpdm_dcc: endpoint {

					slave-mode;

					remote-endpoint =

						<&tpdm_dcc_out_tpda>;

				};

			};



			port@17 {

				reg = <23>;

				tpda_in_tpdm_prng: endpoint {

					slave-mode;
@@ -668,7 +696,7 @@ 
				};

			};



			port@15 {

			port@18 {

				reg = <24>;

				tpda_in_tpdm_qm: endpoint {

					slave-mode;
@@ -677,7 +705,7 @@ 
				};

			};



			port@16 {

			port@19 {

				reg = <25>;

				tpda_in_tpdm_pimem: endpoint {

					slave-mode;
@@ -688,6 +716,26 @@ 
		};

	};



	tpdm_dcc: tpdm@6870000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6870000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-dcc";



		qcom,hw-enable-check;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";



		port {

			tpdm_dcc_out_tpda: endpoint {

				remote-endpoint = <&tpda_in_tpdm_dcc>;

			};

		};

	};



	tpdm_vsense: tpdm@6840000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb968>;
@@ -757,7 +805,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_lpass_out_funnel_dl_center: endpoint {
@@ -878,10 +925,47 @@ 


			port@1 {

				reg = <0>;

				funnel_dl_south_in_tpdm_dl_south: endpoint {

				funnel_dl_south_in_tpda_dl_south: endpoint {

					slave-mode;

					remote-endpoint =

					<&tpda_dl_south_out_funnel_dl_south>;

				};

			};

		};

	};



	tpda_dl_south: tpda@69c1000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb969>;

		reg = <0x69c1000 0x1000>;

		reg-names = "tpda-base";



		coresight-name = "coresight-tpda-dl-south";



		qcom,tpda-atid = <75>;

		qcom,dsb-elem-size = <0 64>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;

			#size-cells = <0>;

			port@0 {

				reg = <0>;

				tpda_dl_south_out_funnel_dl_south: endpoint {

					remote-endpoint =

					<&funnel_dl_south_in_tpda_dl_south>;

				};



			};



			port@1 {

				reg = <0>;

				tpda_dl_south_in_tpdm_dl_south: endpoint {

					slave-mode;

					remote-endpoint =

					<&tpdm_dl_south_out_funnel_dl_south>;

					<&tpdm_dl_south_out_tpda_dl_south>;

				};

			};

		};
@@ -899,9 +983,9 @@ 
		clock-names = "apb_pclk";



		port {

			tpdm_dl_south_out_funnel_dl_south: endpoint {

			tpdm_dl_south_out_tpda_dl_south: endpoint {

				remote-endpoint =

					<&funnel_dl_south_in_tpdm_dl_south>;

					<&tpda_dl_south_in_tpdm_dl_south>;

			};

		};

	};
@@ -921,7 +1005,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_dl_north_out_funnel_in1: endpoint {
@@ -956,7 +1039,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_compute_out_funnel_dl_center: endpoint {
@@ -994,6 +1076,155 @@ 
		};

	};



	tpdm_npu: tpdm@6c47000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb968>;

		reg = <0x6c47000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-npu";



		clocks = <&clock_aop QDSS_CLK>,

			<&clock_gcc GCC_NPU_AXI_CLK>,

			<&clock_gcc GCC_NPU_CFG_AHB_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK_SRC>,

			<&clock_npucc NPU_CC_ATB_CLK>;



		clock-names = "apb_pclk",

			"gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk";



		qcom,proxy-clks = "gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk";



		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-regs ="vdd", "vdd_cx";



		port {

			tpdm_npu_out_funnel_npu: endpoint {

				remote-endpoint = <&funnel_npu_in_tpdm_npu>;

			};

		};

	};



	tpdm_npu_llm: tpdm@6c40000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb968>;

		reg = <0x6c40000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-npu-llm";

		clocks = <&clock_aop QDSS_CLK>,

			<&clock_gcc GCC_NPU_AXI_CLK>,

			<&clock_gcc GCC_NPU_CFG_AHB_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK_SRC>,

			<&clock_npucc NPU_CC_ATB_CLK>,

			<&clock_npucc NPU_CC_LLM_CLK>,

			<&clock_npucc NPU_CC_LLM_XO_CLK>,

			<&clock_npucc NPU_CC_LLM_TEMP_CLK>,

			<&clock_npucc NPU_CC_LLM_CURR_CLK>,

			<&clock_npucc NPU_CC_DL_LLM_CLK>;



		clock-names = "apb_pclk",

			"gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk",

			"npu_cc_llm_clk",

			"npu_cc_llm_xo_clk",

			"npu_cc_llm_temp_clk",

			"npu_cc_llm_curr_clk",

			"npu_cc_dl_llm_clk";



		qcom,proxy-clks = "gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk",

			"npu_cc_llm_clk",

			"npu_cc_llm_xo_clk",

			"npu_cc_llm_temp_clk",

			"npu_cc_llm_curr_clk",

			"npu_cc_dl_llm_clk";



		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-regs ="vdd", "vdd_cx";



		port {

			tpdm_npu_llm_out_funnel_npu: endpoint {

				remote-endpoint = <&funnel_npu_in_tpdm_npu_llm>;

			};

		};

	};



	tpdm_npu_dpm: tpdm@6c41000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb968>;

		reg = <0x6c41000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-npu-dpm";



		clocks = <&clock_aop QDSS_CLK>,

			<&clock_gcc GCC_NPU_AXI_CLK>,

			<&clock_gcc GCC_NPU_CFG_AHB_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK_SRC>,

			<&clock_npucc NPU_CC_ATB_CLK>,

			<&clock_npucc NPU_CC_DPM_CLK>,

			<&clock_npucc NPU_CC_DPM_XO_CLK>,

			<&clock_npucc NPU_CC_DL_DPM_CLK>;



		clock-names = "apb_pclk",

			"gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk",

			"npu_cc_dpm_clk",

			"npu_cc_dpm_xo_clk",

			"npu_cc_dl_dpm_clk";



		qcom,proxy-clks = "gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk",

			"npu_cc_dpm_clk",

			"npu_cc_dpm_xo_clk",

			"npu_cc_dl_dpm_clk";



		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		qcom,proxy-regs ="vdd", "vdd_cx";



		port {

			tpdm_npu_dpm_out_funnel_npu: endpoint {

				remote-endpoint = <&funnel_npu_in_tpdm_npu_dpm>;

			};

		};

	};



	funnel_dl_center: funnel@6c2d000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb908>;
@@ -1009,17 +1240,7 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				tpda_dl_south_out_qatb_3: endpoint {

					remote-endpoint =

					    <&qatb_3_in_tpda_dl_south>;

					source = <&tpdm_dl_south>;

				};

			};



			port@1 {

				reg = <0>;

				tpdm_venus_out_tpda6: endpoint {

					remote-endpoint =
@@ -1028,7 +1249,7 @@ 
				};

			};



			port@2 {

			port@1 {

				reg = <0>;

				tpdm_mdss_out_tpda7: endpoint {

					remote-endpoint =
@@ -1037,7 +1258,7 @@ 
				};

			};



			port@3 {

			port@2 {

				reg = <0>;

				tpdm_mm_out_tpda9: endpoint {

					remote-endpoint =
@@ -1046,7 +1267,7 @@ 
				};

			};



			port@4 {

			port@3 {

				reg = <0>;

				funnel_dl_center_out_tpda_10: endpoint {

					remote-endpoint =
@@ -1055,7 +1276,7 @@ 
				};

			};



			port@5 {

			port@4 {

				reg = <0>;

				tpdm_ddr_ch02_out_tpda11: endpoint {

					remote-endpoint =
@@ -1064,7 +1285,7 @@ 
				};

			};



			port@6 {

			port@5 {

				reg = <0>;

				tpdm_ddr_ch13_out_tpda12: endpoint {

					remote-endpoint =
@@ -1073,7 +1294,7 @@ 
				};

			};



			port@7 {

			port@6 {

				reg = <0>;

				tpdm_ddr_out_tpda13: endpoint {

					remote-endpoint =
@@ -1082,7 +1303,7 @@ 
				};

			};



			port@8 {

			port@7 {

				reg = <0>;

				tpdm_turing_out_tpda14: endpoint {

					remote-endpoint =
@@ -1091,7 +1312,7 @@ 
				};

			};



			port@9 {

			port@8 {

				reg = <0>;

				tpdm_llm_turing_out_tpda15: endpoint {

					remote-endpoint =
@@ -1100,7 +1321,34 @@ 
				};

			};



			port@9 {

				reg = <0>;

				tpdm_npu_out_tpda16: endpoint {

				remote-endpoint =

					<&tpda_16_in_tpdm_npu>;

					source = <&tpdm_npu>;

				};

			};



			port@10 {

				reg = <0>;

				tpdm_npu_llm_out_tpda17: endpoint {

				remote-endpoint =

					<&tpda_17_in_tpdm_npu_llm>;

					source = <&tpdm_npu_llm>;

				};

			};



			port@11 {

				reg = <0>;

				tpdm_npu_dpm_out_tpda18: endpoint {

					remote-endpoint =

					    <&tpda_18_in_tpdm_npu_dpm>;

					source = <&tpdm_npu_dpm>;

				};

			};



			port@12 {

				reg = <0>;

				tpdm_dlct_out_tpda19: endpoint {

					remote-endpoint =
@@ -1109,7 +1357,7 @@ 
				};

			};



			port@11 {

			port@13 {

				reg = <0>;

				tpdm_ipcc_out_tpda20: endpoint {

					remote-endpoint =
@@ -1118,7 +1366,15 @@ 
				};

			};



			port@12 {

			port@14 {

				reg = <0>;

				funnel_dl_center_out_qatb3: endpoint {

					remote-endpoint =

					<&qatb3_in_funnel_dl_center>;

				};

			};



			port@15 {

				reg = <2>;

				funnel_dl_center_in_funnel_dl_mm: endpoint {

					slave-mode;
@@ -1127,7 +1383,7 @@ 
				};

			};



			port@13 {

			port@16 {

				reg = <3>;

				funnel_dl_center_in_funnel_lpass: endpoint {

					slave-mode;
@@ -1136,7 +1392,7 @@ 
				};

			};



			port@14 {

			port@17 {

				reg = <4>;

				funnel_dl_center_in_funnel_ddr_0: endpoint {

					slave-mode;
@@ -1145,7 +1401,7 @@ 
				};

			};



			port@15 {

			port@18 {

				reg = <5>;

				funnel_dl_center_in_funnel_compute: endpoint {

					slave-mode;
@@ -1154,7 +1410,7 @@ 
				};

			};



			port@16 {

			port@19 {

				reg = <6>;

				funnel_center_in_tpdm_dlct: endpoint {

					slave-mode;
@@ -1163,7 +1419,7 @@ 
				};

			};



			port@17 {

			port@20 {

				reg = <7>;

				funnel_center_in_tpdm_ipcc: endpoint {

					slave-mode;
@@ -1385,7 +1641,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_dl_mm_out_funnel_dl_center: endpoint {
@@ -1438,7 +1693,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_venus_out_funnel_dl_mm: endpoint {
@@ -1527,13 +1781,37 @@ 


		coresight-name = "coresight-funnel-npu";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

		clocks = <&clock_aop QDSS_CLK>,

			<&clock_gcc GCC_NPU_AXI_CLK>,

			<&clock_gcc GCC_NPU_CFG_AHB_CLK>,

			<&clock_npucc NPU_CC_XO_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK>,

			<&clock_npucc NPU_CC_CORE_CLK_SRC>,

			<&clock_npucc NPU_CC_ATB_CLK>;



		clock-names = "apb_pclk",

			"gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk";



		qcom,proxy-clks = "gcc_npu_axi_clk",

			"gcc_npu_cfg_ahb_clk",

			"npu_cc_xo_clk",

			"npu_core_clk",

			"npu_core_clk_src",

			"npu_cc_atb_clk";



		vdd-supply = <&npu_core_gdsc>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		regulator-names = "vdd", "vdd_cx";

		qcom,proxy-regs ="vdd", "vdd_cx";



		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_npu_out_funnel_dl_compute: endpoint {
@@ -1543,6 +1821,33 @@ 
			};



			port@1 {

				reg = <0>;

				funnel_npu_in_tpdm_npu: endpoint {

					slave-mode;

					remote-endpoint =

						<&tpdm_npu_out_funnel_npu>;

				};

			};



			port@2 {

				reg = <1>;

				funnel_npu_in_tpdm_npu_llm: endpoint {

					slave-mode;

					remote-endpoint =

						<&tpdm_npu_llm_out_funnel_npu>;

				};

			};



			port@3 {

				reg = <2>;

				funnel_npu_in_tpdm_npu_dpm: endpoint {

					slave-mode;

					remote-endpoint =

					    <&tpdm_npu_dpm_out_funnel_npu>;

				};

			};



			port@4 {

				reg = <3>;

				funnel_npu_in_npu_etm0: endpoint {

					slave-mode;
@@ -1568,7 +1873,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_turing_out_funnel_dl_compute: endpoint {
@@ -1633,7 +1937,7 @@ 
		reg = <0x6981000 0x1000>;

		reg-names = "tpdm-base";



		coresight-name = "coresight-tpdm-llm-turing";

		coresight-name = "coresight-tpdm-turing-llm";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -1661,7 +1965,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_ddr_0_out_funnel_dl_center: endpoint {
@@ -1714,7 +2017,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_ddr_ch02_out_funnel_ddr_0: endpoint {
@@ -1749,7 +2051,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_ddr_ch13_out_funnel_ddr_0: endpoint {
@@ -1846,7 +2147,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_qatb_out_funnel_in0: endpoint {
@@ -1866,10 +2166,10 @@ 


			port@2 {

				reg = <3>;

				qatb_3_in_tpda_dl_south: endpoint {

				qatb3_in_funnel_dl_center: endpoint {

					slave-mode;

					remote-endpoint =

					    <&tpda_dl_south_out_qatb_3>;

					    <&funnel_dl_center_out_qatb3>;

				};

			};

		};
@@ -2411,7 +2711,7 @@ 
		clock-names = "apb_pclk";

	};



	turing_etm0 {

	etm_turing: turing_etm0 {

		compatible = "qcom,coresight-remote-etm";



		coresight-name = "coresight-turing-etm0";
@@ -2482,7 +2782,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_apss_merg_out_funnel_in1: endpoint {
@@ -2687,7 +2986,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_apss_out_funnel_apss_merg: endpoint {