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Commit 4b7b2331 authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Paulo Zanoni
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drm/i915/kbl: IPC workaround for kabylake 



Display Workarounds #1141
IPC (Isoch Priority Control) may cause underflows.

KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.

Changes since V1:
 - Add Workaround number in commit & code
Changes since V2 (from Paulo):
 - Bikeshed the WA tag so it looks like the others

Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161201154940.24446-4-mahesh1.kumar@intel.com
parent a3a8986c

drivers/gpu/drm/i915/intel_pm.c

+4 −0
Original line number Diff line number Diff line
@@ -3596,6 +3596,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 
		  fb->modifier == I915_FORMAT_MOD_Yf_TILED;

	x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;



	/* Display WA #1141: kbl. */

	if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled)

		latency += 4;



	if (apply_memory_bw_wa && x_tiled)

		latency += 15;