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Commit 4b472ffd authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: Enable ARM64_HARDEN_EL2_VECTORS on Cortex-A57 and A72 



Cortex-A57 and A72 are vulnerable to the so-called "variant 3a" of
Meltdown, where an attacker can speculatively obtain the value
of a privileged system register.

By enabling ARM64_HARDEN_EL2_VECTORS on these CPUs, obtaining
VBAR_EL2 is not disclosing the hypervisor mappings anymore.

Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent dee39247

arch/arm64/kernel/cpu_errata.c

+12 −0
Original line number Diff line number Diff line
@@ -424,6 +424,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),

		.enable = enable_smccc_arch_workaround_1,

	},

#endif

#ifdef CONFIG_HARDEN_EL2_VECTORS

	{

		.desc = "Cortex-A57 EL2 vector hardening",

		.capability = ARM64_HARDEN_EL2_VECTORS,

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

	},

	{

		.desc = "Cortex-A72 EL2 vector hardening",

		.capability = ARM64_HARDEN_EL2_VECTORS,

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

	},

#endif

	{

	}