Commit 4b36f1a4 authored Jun 11, 2015 by Andi Kleen Committed by Ingo Molnar Jun 19, 2015

perf/x86: Add more Broadwell model numbers

This patch adds additional model numbers for Broadwell to perf.
Support for Broadwell with Iris Pro (Intel Core i7-57xxC)
and support for Broadwell Server Xeon.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1434055942-28253-1-git-send-email-andi@firstfloor.org

Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent 2f993cf0

arch/x86/kernel/cpu/perf_event_intel.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -3253,6 +3253,8 @@ __init int intel_pmu_init(void)

		case 61: /* 14nm Broadwell Core-M */
		case 86: /* 14nm Broadwell Xeon D */
		case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
		case 79: /* 14nm Broadwell Server */
		x86_pmu.late_ack = true;
		memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
		memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));