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Commit 4af0fa39 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Move GBIF/VBIF settings to the GPU list"

parents 35bfdb57 03e92d7e

drivers/gpu/msm/adreno-gpulist.h

+1122 −314

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/msm/adreno.c

+34 −44
Original line number Original line Diff line number Diff line
@@ -30,8 +30,10 @@ 
#include "adreno_pm4types.h"

#include "adreno_pm4types.h"

#include "adreno_trace.h"

#include "adreno_trace.h"





#include "a3xx_reg.h"

#include "adreno_a3xx.h"

#include "a6xx_reg.h"

#include "adreno_a5xx.h"

#include "adreno_a6xx.h"



#include "adreno_snapshot.h"

#include "adreno_snapshot.h"





/* Include the master list of GPU cores that are supported */

/* Include the master list of GPU cores that are supported */
@@ -106,6 +108,16 @@ int adreno_wake_nice = -7; 
/* Number of milliseconds to stay active active after a wake on touch */

/* Number of milliseconds to stay active active after a wake on touch */

unsigned int adreno_wake_timeout = 100;

unsigned int adreno_wake_timeout = 100;





void adreno_reglist_write(struct adreno_device *adreno_dev,

		const struct adreno_reglist *list, u32 count)

{

	int i;



	for (i = 0; list && i < count; i++)

		kgsl_regwrite(KGSL_DEVICE(adreno_dev),

			list[i].offset, list[i].value);

}



/**

/**

 * adreno_readreg64() - Read a 64bit register by getting its offset from the

 * adreno_readreg64() - Read a 64bit register by getting its offset from the

 * offset array defined in gpudev node

 * offset array defined in gpudev node
@@ -684,11 +696,11 @@ static inline const struct adreno_gpu_core *_get_gpu_core(unsigned int chipid) 
	int i;

	int i;





	for (i = 0; i < ARRAY_SIZE(adreno_gpulist); i++) {

	for (i = 0; i < ARRAY_SIZE(adreno_gpulist); i++) {

		if (core == adreno_gpulist[i].core &&

		if (core == adreno_gpulist[i]->core &&

		    _rev_match(major, adreno_gpulist[i].major) &&

		    _rev_match(major, adreno_gpulist[i]->major) &&

		    _rev_match(minor, adreno_gpulist[i].minor) &&

		    _rev_match(minor, adreno_gpulist[i]->minor) &&

		    _rev_match(patchid, adreno_gpulist[i].patchid))

		    _rev_match(patchid, adreno_gpulist[i]->patchid))

			return &adreno_gpulist[i];

			return adreno_gpulist[i];

	}

	}





	return NULL;

	return NULL;
@@ -1629,23 +1641,6 @@ static int adreno_init(struct kgsl_device *device) 




	set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);

	set_bit(ADRENO_DEVICE_INITIALIZED, &adreno_dev->priv);





	/* Use shader offset and length defined in gpudev */

	if (adreno_dev->gpucore->shader_offset &&

					adreno_dev->gpucore->shader_size) {



		if (device->shader_mem_phys || device->shader_mem_virt)

			dev_err(device->dev,

				     "Shader memory already specified in device tree\n");

		else {

			device->shader_mem_phys = device->reg_phys +

					adreno_dev->gpucore->shader_offset;

			device->shader_mem_virt = device->reg_virt +

					adreno_dev->gpucore->shader_offset;

			device->shader_mem_len =

					adreno_dev->gpucore->shader_size;

		}

	}



	/*

	/*

	 * Allocate a small chunk of memory for precise drawobj profiling for

	 * Allocate a small chunk of memory for precise drawobj profiling for

	 * those targets that have the always on timer

	 * those targets that have the always on timer
@@ -2365,25 +2360,6 @@ static int adreno_prop_ucode_version(struct kgsl_device *device, 
	return copy_prop(param, &ucode, sizeof(ucode));

	return copy_prop(param, &ucode, sizeof(ucode));

}

}





static int adreno_prop_gpmu_version(struct kgsl_device *device,

		struct kgsl_device_getproperty *param)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct kgsl_gpmu_version gpmu = { 0 };



	if (!adreno_dev->gpucore)

		return -EINVAL;



	if (!ADRENO_FEATURE(adreno_dev, ADRENO_GPMU))

		return -EOPNOTSUPP;



	gpmu.major = adreno_dev->gpucore->gpmu_major;

	gpmu.minor = adreno_dev->gpucore->gpmu_minor;

	gpmu.features = adreno_dev->gpucore->gpmu_features;



	return copy_prop(param, &gpmu, sizeof(gpmu));

}



static int adreno_prop_u32(struct kgsl_device *device,

static int adreno_prop_u32(struct kgsl_device *device,

		struct kgsl_device_getproperty *param)

		struct kgsl_device_getproperty *param)

{

{
@@ -2421,7 +2397,6 @@ static const struct { 
	{ KGSL_PROP_INTERRUPT_WAITS, adreno_prop_s32 },

	{ KGSL_PROP_INTERRUPT_WAITS, adreno_prop_s32 },

	{ KGSL_PROP_UCHE_GMEM_VADDR, adreno_prop_uche_gmem_addr },

	{ KGSL_PROP_UCHE_GMEM_VADDR, adreno_prop_uche_gmem_addr },

	{ KGSL_PROP_UCODE_VERSION, adreno_prop_ucode_version },

	{ KGSL_PROP_UCODE_VERSION, adreno_prop_ucode_version },

	{ KGSL_PROP_GPMU_VERSION, adreno_prop_gpmu_version },

	{ KGSL_PROP_HIGHEST_BANK_BIT, adreno_prop_u32 },

	{ KGSL_PROP_HIGHEST_BANK_BIT, adreno_prop_u32 },

	{ KGSL_PROP_MIN_ACCESS_LENGTH, adreno_prop_u32 },

	{ KGSL_PROP_MIN_ACCESS_LENGTH, adreno_prop_u32 },

	{ KGSL_PROP_UBWC_MODE, adreno_prop_u32 },

	{ KGSL_PROP_UBWC_MODE, adreno_prop_u32 },
@@ -2442,6 +2417,20 @@ static int adreno_getproperty(struct kgsl_device *device, 
	return -ENODEV;

	return -ENODEV;

}

}





static int adreno_query_property_list(struct kgsl_device *device, u32 *list,

		u32 count)

{

	int i;



	if (!list)

		return ARRAY_SIZE(adreno_property_funcs);



	for (i = 0; i < count && i < ARRAY_SIZE(adreno_property_funcs); i++)

		list[i] = adreno_property_funcs[i].type;



	return i;

}



int adreno_set_constraint(struct kgsl_device *device,

int adreno_set_constraint(struct kgsl_device *device,

				struct kgsl_context *context,

				struct kgsl_context *context,

				struct kgsl_device_constraint *constraint)

				struct kgsl_device_constraint *constraint)
@@ -3750,6 +3739,7 @@ static const struct kgsl_functable adreno_functable = { 
	.stop_fault_timer = adreno_dispatcher_stop_fault_timer,

	.stop_fault_timer = adreno_dispatcher_stop_fault_timer,

	.dispatcher_halt = adreno_dispatcher_halt,

	.dispatcher_halt = adreno_dispatcher_halt,

	.dispatcher_unhalt = adreno_dispatcher_unhalt,

	.dispatcher_unhalt = adreno_dispatcher_unhalt,

	.query_property_list = adreno_query_property_list,

};

};





static struct platform_driver adreno_platform_driver = {

static struct platform_driver adreno_platform_driver = {

drivers/gpu/msm/adreno.h

+19 −77
Original line number Original line Diff line number Diff line
@@ -336,6 +336,16 @@ struct adreno_device_private { 
	struct list_head perfcounter_list;

	struct list_head perfcounter_list;

};

};





/**

 * struct adreno_reglist - simple container for register offsets / values

 */

struct adreno_reglist {

	/** @offset: Offset of the register */

	u32 offset;

	/** @value: Default value of the register to write */

	u32 value;

};



/**

/**

 * struct adreno_gpu_core - A specific GPU core definition

 * struct adreno_gpu_core - A specific GPU core definition

 * @gpurev: Unique GPU revision identifier

 * @gpurev: Unique GPU revision identifier
@@ -344,54 +354,23 @@ struct adreno_device_private { 
 * @minor: Match for the minor version of the GPU

 * @minor: Match for the minor version of the GPU

 * @patchid: Match for the patch revision of the GPU

 * @patchid: Match for the patch revision of the GPU

 * @features: Common adreno features supported by this core

 * @features: Common adreno features supported by this core

 * @pm4fw_name: Filename for th PM4 firmware

 * @pfpfw_name: Filename for the PFP firmware

 * @zap_name: Filename for the Zap Shader ucode

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gpudev: Pointer to the GPU family specific functions for this core

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_base: Base address of binning memory (GMEM/OCMEM)

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @gmem_size: Amount of binning memory (GMEM/OCMEM) to reserve for the core

 * @shader_offset: Offset of shader from gpu reg base

 * @shader_size: Shader size

 * @num_protected_regs: number of protected registers

 * @num_protected_regs: number of protected registers

 * @gpmufw_name: Filename for the GPMU firmware

 * @gpmu_major: Match for the GPMU & firmware, major revision

 * @gpmu_minor: Match for the GPMU & firmware, minor revision

 * @gpmu_features: Supported features for any given GPMU version

 * @busy_mask: mask to check if GPU is busy in RBBM_STATUS

 * @busy_mask: mask to check if GPU is busy in RBBM_STATUS

 * @lm_major: Limits Management register sequence, major revision

 * @lm_minor: LM register sequence, minor revision

 * @regfw_name: Filename for the register sequence firmware

 * @gpmu_tsens: ID for the temporature sensor used by the GPMU

 * @max_power: Max possible power draw of a core, units elephant tail hairs

 */

 */

struct adreno_gpu_core {

struct adreno_gpu_core {

	enum adreno_gpurev gpurev;

	enum adreno_gpurev gpurev;

	unsigned int core, major, minor, patchid;

	unsigned int core, major, minor, patchid;

	unsigned long features;

	unsigned long features;

	const char *pm4fw_name;

	const char *pfpfw_name;

	const char *sqefw_name;

	const char *zap_name;

	struct adreno_gpudev *gpudev;

	struct adreno_gpudev *gpudev;

	unsigned long gmem_base;

	unsigned long gmem_base;

	size_t gmem_size;

	size_t gmem_size;

	unsigned long shader_offset;

	unsigned int shader_size;

	unsigned int num_protected_regs;

	unsigned int num_protected_regs;

	const char *gpmufw_name;

	unsigned int gpmu_major;

	unsigned int gpmu_minor;

	unsigned int gpmu_features;

	unsigned int busy_mask;

	unsigned int busy_mask;

	unsigned int lm_major, lm_minor;

	const char *regfw_name;

	unsigned int gpmu_tsens;

	unsigned int max_power;

	unsigned int prim_fifo_threshold;

	unsigned int pdc_address_offset;

};

};







enum gpu_coresight_sources {

enum gpu_coresight_sources {

	GPU_CORESIGHT_GX = 0,

	GPU_CORESIGHT_GX = 0,

	GPU_CORESIGHT_CX = 1,

	GPU_CORESIGHT_CX = 1,
@@ -762,27 +741,6 @@ struct adreno_reg_offsets { 
#define ADRENO_REG_DEFINE(_offset, _reg)[_offset] = _reg

#define ADRENO_REG_DEFINE(_offset, _reg)[_offset] = _reg

#define ADRENO_INT_DEFINE(_offset, _val) ADRENO_REG_DEFINE(_offset, _val)

#define ADRENO_INT_DEFINE(_offset, _val) ADRENO_REG_DEFINE(_offset, _val)





/*

 * struct adreno_vbif_data - Describes vbif register value pair

 * @reg: Offset to vbif register

 * @val: The value that should be programmed in the register at reg

 */

struct adreno_vbif_data {

	unsigned int reg;

	unsigned int val;

};



/*

 * struct adreno_vbif_platform - Holds an array of vbif reg value pairs

 * for a particular core

 * @devfunc: Pointer to platform/core identification function

 * @vbif: Array of reg value pairs for vbif registers

 */

struct adreno_vbif_platform {

	int (*devfunc)(struct adreno_device *adreno_dev);

	const struct adreno_vbif_data *vbif;

};



/*

/*

 * struct adreno_vbif_snapshot_registers - Holds an array of vbif registers

 * struct adreno_vbif_snapshot_registers - Holds an array of vbif registers

 * listed for snapshot dump for a particular core

 * listed for snapshot dump for a particular core
@@ -1488,32 +1446,16 @@ static inline void adreno_put_gpu_halt(struct adreno_device *adreno_dev) 
}

}









/*

/**

 * adreno_vbif_start() - Program VBIF registers, called in device start

 * adreno_reglist_write - Write each register in a reglist

 * @adreno_dev: Pointer to device whose vbif data is to be programmed

 * @adreno_dev: An Adreno GPU device handle

 * @vbif_platforms: list register value pair of vbif for a family

 * @reglist: A list of &struct adreno_reglist items

 * of adreno cores

 * @count: Number of items in @reglist

 * @num_platforms: Number of platforms contained in vbif_platforms

 *

 * Write each register listed in @reglist.

 */

 */

static inline void adreno_vbif_start(struct adreno_device *adreno_dev,

void adreno_reglist_write(struct adreno_device *adreno_dev,

			const struct adreno_vbif_platform *vbif_platforms,

		const struct adreno_reglist *list, u32 count);

			int num_platforms)

{

	int i;

	const struct adreno_vbif_data *vbif = NULL;



	for (i = 0; i < num_platforms; i++) {

		if (vbif_platforms[i].devfunc(adreno_dev)) {

			vbif = vbif_platforms[i].vbif;

			break;

		}

	}



	while ((vbif != NULL) && (vbif->reg != 0)) {

		kgsl_regwrite(KGSL_DEVICE(adreno_dev), vbif->reg, vbif->val);

		vbif++;

	}

}





/**

/**

 * adreno_set_protected_registers() - Protect the specified range of registers

 * adreno_set_protected_registers() - Protect the specified range of registers

drivers/gpu/msm/adreno_a3xx.c

+9 −32
Original line number Original line Diff line number Diff line
@@ -831,32 +831,6 @@ static struct adreno_irq a3xx_irq = { 
	.mask = A3XX_INT_MASK,

	.mask = A3XX_INT_MASK,

};

};





/* VBIF registers start after 0x3000 so use 0x0 as end of list marker */

static const struct adreno_vbif_data a304_vbif[] = {

	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },

	{0, 0},

};



static const struct adreno_vbif_data a306_vbif[] = {

	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },

	{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000A },

	{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000A },

	{0, 0},

};



static const struct adreno_vbif_data a306a_vbif[] = {

	{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },

	{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010 },

	{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010 },

	{0, 0},

};



static const struct adreno_vbif_platform a3xx_vbif_platforms[] = {

	{ adreno_is_a304, a304_vbif },

	{ adreno_is_a306, a306_vbif },

	{ adreno_is_a306a, a306a_vbif },

};



/*

/*

 * Define the available perfcounter groups - these get used by

 * Define the available perfcounter groups - these get used by

 * adreno_perfcounter_get and adreno_perfcounter_put

 * adreno_perfcounter_get and adreno_perfcounter_put
@@ -1157,9 +1131,11 @@ static void a3xx_protect_init(struct adreno_device *adreno_dev) 
static void a3xx_start(struct adreno_device *adreno_dev)

static void a3xx_start(struct adreno_device *adreno_dev)

{

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	const struct adreno_a3xx_core *a3xx_core = to_a3xx_core(adreno_dev);





	adreno_vbif_start(adreno_dev, a3xx_vbif_platforms,

	/* Set up VBIF registers from the GPU core definition */

			ARRAY_SIZE(a3xx_vbif_platforms));

	adreno_reglist_write(adreno_dev, a3xx_core->vbif,

		a3xx_core->vbif_count);





	/* Make all blocks contribute to the GPU BUSY perf counter */

	/* Make all blocks contribute to the GPU BUSY perf counter */

	kgsl_regwrite(device, A3XX_RBBM_GPU_BUSY_MASKED, 0xFFFFFFFF);

	kgsl_regwrite(device, A3XX_RBBM_GPU_BUSY_MASKED, 0xFFFFFFFF);
@@ -1394,17 +1370,18 @@ static int a3xx_microcode_read(struct adreno_device *adreno_dev) 
	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);

	struct adreno_firmware *pm4_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PM4);

	struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);

	struct adreno_firmware *pfp_fw = ADRENO_FW(adreno_dev, ADRENO_FW_PFP);

	const struct adreno_a3xx_core *a3xx_core = to_a3xx_core(adreno_dev);





	if (pm4_fw->fwvirt == NULL) {

	if (pm4_fw->fwvirt == NULL) {

		int len;

		int len;

		void *ptr;

		void *ptr;





		int ret = _load_firmware(device,

		int ret = _load_firmware(device,

			adreno_dev->gpucore->pm4fw_name, &ptr, &len);

			a3xx_core->pm4fw_name, &ptr, &len);





		if (ret) {

		if (ret) {

			dev_err(device->dev,  "Failed to read pm4 ucode %s\n",

			dev_err(device->dev,  "Failed to read pm4 ucode %s\n",

				adreno_dev->gpucore->pm4fw_name);

				a3xx_core->pm4fw_name);

			return ret;

			return ret;

		}

		}
@@ -1427,10 +1404,10 @@ static int a3xx_microcode_read(struct adreno_device *adreno_dev) 
		void *ptr;

		void *ptr;





		int ret = _load_firmware(device,

		int ret = _load_firmware(device,

			adreno_dev->gpucore->pfpfw_name, &ptr, &len);

			a3xx_core->pfpfw_name, &ptr, &len);

		if (ret) {

		if (ret) {

			dev_err(device->dev, "Failed to read pfp ucode %s\n",

			dev_err(device->dev, "Failed to read pfp ucode %s\n",

					   adreno_dev->gpucore->pfpfw_name);

					   a3xx_core->pfpfw_name);

			return ret;

			return ret;

		}

		}

drivers/gpu/msm/adreno_a3xx.h

+30 −0
Original line number Original line Diff line number Diff line
@@ -6,6 +6,21 @@ 
#define __A3XX_H

#define __A3XX_H





#include "a3xx_reg.h"

#include "a3xx_reg.h"

/**

 * struct adreno_a3xx_core - a3xx specific GPU core definitions

 */

struct adreno_a3xx_core {

	/** @base: Container for the generic &struct adreno_gpu_core */

	struct adreno_gpu_core base;

	/** pm4fw_name: Name of the PM4 microcode file */

	const char *pm4fw_name;

	/** pfpfw_name: Name of the PFP microcode file */

	const char *pfpfw_name;

	/** @vbif: List of registers and values to write for VBIF */

	const struct adreno_reglist *vbif;

	/** @vbif_count: Number of registers in @vbif */

	u32 vbif_count;

};





#define A3XX_IRQ_FLAGS \

#define A3XX_IRQ_FLAGS \

	{ BIT(A3XX_INT_RBBM_GPU_IDLE), "RBBM_GPU_IDLE" }, \

	{ BIT(A3XX_INT_RBBM_GPU_IDLE), "RBBM_GPU_IDLE" }, \
@@ -33,6 +48,21 @@ 
	{ BIT(A3XX_INT_MISC_HANG_DETECT), "MISC_HANG_DETECT" }, \

	{ BIT(A3XX_INT_MISC_HANG_DETECT), "MISC_HANG_DETECT" }, \

	{ BIT(A3XX_INT_UCHE_OOB_ACCESS), "UCHE_OOB_ACCESS" }

	{ BIT(A3XX_INT_UCHE_OOB_ACCESS), "UCHE_OOB_ACCESS" }





/**

 * to_a3xx_core - return the a3xx specific GPU core struct

 * @adreno_dev: An Adreno GPU device handle

 *

 * Returns:

 * A pointer to the a3xx specific GPU core struct

 */

static inline const struct adreno_a3xx_core *

to_a3xx_core(struct adreno_device *adreno_dev)

{

	const struct adreno_gpu_core *core = adreno_dev->gpucore;



	return container_of(core, struct adreno_a3xx_core, base);

}



unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev);

unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev);





void a3xx_snapshot(struct adreno_device *adreno_dev,

void a3xx_snapshot(struct adreno_device *adreno_dev,