Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4ad79562 authored by Joerg Roedel's avatar Joerg Roedel
Browse files

Merge branches 'arm/omap', 'arm/msm', 'arm/smmu', 'arm/tegra', 'x86/vt-d',... 

Merge branches 'arm/omap', 'arm/msm', 'arm/smmu', 'arm/tegra', 'x86/vt-d', 'x86/amd', 'ppc/pamu' and 'core' into next
parents c13dcf9f e203db29 6e6cfbc8 cf27ec93 54e466fd 4df4eab1 23d3a98c 57fb907d 7b0ce727

Documentation/Intel-IOMMU.txt

+1 −1
Original line number Original line Diff line number Diff line
@@ -10,7 +10,7 @@ This guide gives a quick cheat sheet for some basic understanding. 
Some Keywords

Some Keywords





DMAR - DMA remapping

DMAR - DMA remapping

DRHD - DMA Engine Reporting Structure

DRHD - DMA Remapping Hardware Unit Definition

RMRR - Reserved memory Region Reporting Structure

RMRR - Reserved memory Region Reporting Structure

ZLR  - Zero length reads from PCI devices

ZLR  - Zero length reads from PCI devices

IOVA - IO Virtual address.

IOVA - IO Virtual address.

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+6 −0
Original line number Original line Diff line number Diff line
@@ -43,6 +43,12 @@ conditions. 




** System MMU optional properties:

** System MMU optional properties:





- dma-coherent  : Present if page table walks made by the SMMU are

                  cache coherent with the CPU.



                  NOTE: this only applies to the SMMU itself, not

                  masters connected upstream of the SMMU.



- calxeda,smmu-secure-config-access : Enable proper handling of buggy

- calxeda,smmu-secure-config-access : Enable proper handling of buggy

                  implementations that always use secure access to

                  implementations that always use secure access to

                  SMMU configuration registers. In this case non-secure

                  SMMU configuration registers. In this case non-secure

Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt

+6 −0
Original line number Original line Diff line number Diff line
@@ -8,6 +8,11 @@ Required properties: 
- ti,hwmods  : Name of the hwmod associated with the IOMMU instance

- ti,hwmods  : Name of the hwmod associated with the IOMMU instance

- reg        : Address space for the configuration registers

- reg        : Address space for the configuration registers

- interrupts : Interrupt specifier for the IOMMU instance

- interrupts : Interrupt specifier for the IOMMU instance

- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,

                 and needs no additional data in the pargs specifier. Please

                 also refer to the generic bindings document for more info

                 on this property,

                     Documentation/devicetree/bindings/iommu/iommu.txt





Optional properties:

Optional properties:

- ti,#tlb-entries : Number of entries in the translation look-aside buffer.

- ti,#tlb-entries : Number of entries in the translation look-aside buffer.
@@ -18,6 +23,7 @@ Optional properties: 
Example:

Example:

	/* OMAP3 ISP MMU */

	/* OMAP3 ISP MMU */

	mmu_isp: mmu@480bd400 {

	mmu_isp: mmu@480bd400 {

		#iommu-cells = <0>;

		compatible = "ti,omap2-iommu";

		compatible = "ti,omap2-iommu";

		reg = <0x480bd400 0x80>;

		reg = <0x480bd400 0x80>;

		interrupts = <24>;

		interrupts = <24>;

drivers/iommu/Kconfig

+2 −1
Original line number Original line Diff line number Diff line
@@ -23,7 +23,8 @@ config IOMMU_IO_PGTABLE 
config IOMMU_IO_PGTABLE_LPAE

config IOMMU_IO_PGTABLE_LPAE

	bool "ARMv7/v8 Long Descriptor Format"

	bool "ARMv7/v8 Long Descriptor Format"

	select IOMMU_IO_PGTABLE

	select IOMMU_IO_PGTABLE

	depends on ARM || ARM64 || COMPILE_TEST

	# SWIOTLB guarantees a dma_to_phys() implementation

	depends on ARM || ARM64 || (COMPILE_TEST && SWIOTLB)

	help

	help

	  Enable support for the ARM long descriptor pagetable format.

	  Enable support for the ARM long descriptor pagetable format.

	  This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page

	  This allocator supports 4K/2M/1G, 16K/32M and 64K/512M page

drivers/iommu/amd_iommu.c

+8 −13
Original line number Original line Diff line number Diff line
@@ -1835,8 +1835,8 @@ static void free_gcr3_table(struct protection_domain *domain) 
		free_gcr3_tbl_level2(domain->gcr3_tbl);

		free_gcr3_tbl_level2(domain->gcr3_tbl);

	else if (domain->glx == 1)

	else if (domain->glx == 1)

		free_gcr3_tbl_level1(domain->gcr3_tbl);

		free_gcr3_tbl_level1(domain->gcr3_tbl);

	else if (domain->glx != 0)

	else

		BUG();

		BUG_ON(domain->glx != 0);





	free_page((unsigned long)domain->gcr3_tbl);

	free_page((unsigned long)domain->gcr3_tbl);

}

}
@@ -3947,11 +3947,6 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, 
	if (ret < 0)

	if (ret < 0)

		return ret;

		return ret;





	ret = -ENOMEM;

	data = kzalloc(sizeof(*data), GFP_KERNEL);

	if (!data)

		goto out_free_parent;



	if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {

	if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {

		if (get_irq_table(devid, true))

		if (get_irq_table(devid, true))

			index = info->ioapic_pin;

			index = info->ioapic_pin;
@@ -3962,7 +3957,6 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, 
	}

	}

	if (index < 0) {

	if (index < 0) {

		pr_warn("Failed to allocate IRTE\n");

		pr_warn("Failed to allocate IRTE\n");

		kfree(data);

		goto out_free_parent;

		goto out_free_parent;

	}

	}
@@ -3974,17 +3968,18 @@ static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq, 
			goto out_free_data;

			goto out_free_data;

		}

		}





		if (i > 0) {

		ret = -ENOMEM;

		data = kzalloc(sizeof(*data), GFP_KERNEL);

		data = kzalloc(sizeof(*data), GFP_KERNEL);

		if (!data)

		if (!data)

			goto out_free_data;

			goto out_free_data;

		}



		irq_data->hwirq = (devid << 16) + i;

		irq_data->hwirq = (devid << 16) + i;

		irq_data->chip_data = data;

		irq_data->chip_data = data;

		irq_data->chip = &amd_ir_chip;

		irq_data->chip = &amd_ir_chip;

		irq_remapping_prepare_irte(data, cfg, info, devid, index, i);

		irq_remapping_prepare_irte(data, cfg, info, devid, index, i);

		irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);

		irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);

	}

	}



	return 0;

	return 0;





out_free_data:

out_free_data: