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Commit 4ad3e363 authored by Marc Zyngier's avatar Marc Zyngier Committed by Jason Cooper
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irqchip: gicv3-its: Fix PROP/PEND and BASE/CBASE confusion 



The ITS driver sometime mixes up the use of GICR_PROPBASE bitfields
for the GICR_PENDBASE register, and GITS_BASER for GICR_CBASE.

This does not lead to any observable bug because similar bits are
at the same location, but this just make the code even harder to
understand...

This patch provides the required #defines and fixes the mixup.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1427465705-17126-4-git-send-email-marc.zyngier@arm.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 7e195ba0

drivers/irqchip/irq-gic-v3-its.c

+3 −3
Original line number Diff line number Diff line
@@ -986,8 +986,8 @@ static void its_cpu_init_lpis(void) 


	/* set PENDBASE */

	val = (page_to_phys(pend_page) |

	       GICR_PROPBASER_InnerShareable |

	       GICR_PROPBASER_WaWb);

	       GICR_PENDBASER_InnerShareable |

	       GICR_PENDBASER_WaWb);



	writeq_relaxed(val, rbase + GICR_PENDBASER);
@@ -1425,7 +1425,7 @@ static int its_probe(struct device_node *node, struct irq_domain *parent) 
	writeq_relaxed(0, its->base + GITS_CWRITER);

	writel_relaxed(GITS_CTLR_ENABLE, its->base + GITS_CTLR);



	if ((tmp ^ baser) & GITS_BASER_SHAREABILITY_MASK) {

	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {

		pr_info("ITS: using cache flushing for cmd queue\n");

		its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;

	}

include/linux/irqchip/arm-gic-v3.h

+13 −0
Original line number Diff line number Diff line
@@ -128,6 +128,19 @@ 
#define GICR_PROPBASER_RaWaWb		(7U << 7)

#define GICR_PROPBASER_IDBITS_MASK	(0x1f)



#define GICR_PENDBASER_NonShareable	(0U << 10)

#define GICR_PENDBASER_InnerShareable	(1U << 10)

#define GICR_PENDBASER_OuterShareable	(2U << 10)

#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)

#define GICR_PENDBASER_nCnB		(0U << 7)

#define GICR_PENDBASER_nC		(1U << 7)

#define GICR_PENDBASER_RaWt		(2U << 7)

#define GICR_PENDBASER_RaWb		(3U << 7)

#define GICR_PENDBASER_WaWt		(4U << 7)

#define GICR_PENDBASER_WaWb		(5U << 7)

#define GICR_PENDBASER_RaWaWt		(6U << 7)

#define GICR_PENDBASER_RaWaWb		(7U << 7)



/*

 * Re-Distributor registers, offsets from SGI_base

 */