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Commit 4aa4c23f authored by Carlos Santa's avatar Carlos Santa Committed by Rodrigo Vivi
Browse files

drm/i915: Move HAS_RUNTIME_PM definition to platform 



Moving all GPU features to the platform struct definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: default avatarCarlos Santa <carlos.santa@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 07db6be7

drivers/gpu/drm/i915/i915_drv.h

+2 −4
Original line number Diff line number Diff line
@@ -655,6 +655,7 @@ struct intel_csr { 
	func(is_preliminary) sep \

	func(has_fbc) sep \

	func(has_psr) sep \

	func(has_runtime_pm) sep \

	func(has_pipe_cxsr) sep \

	func(has_hotplug) sep \

	func(cursor_needs_physical) sep \
@@ -2786,10 +2787,7 @@ struct drm_i915_cmd_table { 
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)

#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)

#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)

#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \

				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \

				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \

				 IS_KABYLAKE(dev) || IS_BROXTON(dev))

#define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)

#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)

#define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))

drivers/gpu/drm/i915/i915_pci.c

+6 −1
Original line number Diff line number Diff line
@@ -199,6 +199,7 @@ static const struct intel_device_info intel_ironlake_m_info = { 
	.gen = 6, .num_pipes = 2, \

	.need_gfx_hws = 1, .has_hotplug = 1, \

	.has_fbc = 1, \

	.has_runtime_pm = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.has_llc = 1, \

	GEN_DEFAULT_PIPEOFFSETS, \
@@ -242,6 +243,7 @@ static const struct intel_device_info intel_ivybridge_q_info = { 
#define VLV_FEATURES  \

	.gen = 7, .num_pipes = 2, \

	.has_psr = 1, \

	.has_runtime_pm = 1, \

	.need_gfx_hws = 1, .has_hotplug = 1, \

	.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \

	.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -258,7 +260,8 @@ static const struct intel_device_info intel_valleyview_info = { 
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \

	.has_ddi = 1, \

	.has_fpga_dbg = 1, \

	.has_psr = 1

	.has_psr = 1, \

	.has_runtime_pm = 1



static const struct intel_device_info intel_haswell_info = {

	HSW_FEATURES,
@@ -288,6 +291,7 @@ static const struct intel_device_info intel_cherryview_info = { 
	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,

	.is_cherryview = 1,

	.has_psr = 1,

	.has_runtime_pm = 1,

	.display_mmio_offset = VLV_DISPLAY_BASE,

	GEN_CHV_PIPEOFFSETS,

	CURSOR_OFFSETS,
@@ -316,6 +320,7 @@ static const struct intel_device_info intel_broxton_info = { 
	.has_ddi = 1,

	.has_fpga_dbg = 1,

	.has_fbc = 1,

	.has_runtime_pm = 1,

	.has_pooled_eu = 0,

	GEN_DEFAULT_PIPEOFFSETS,

	IVB_CURSOR_OFFSETS,