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Commit 4a9f5262 authored by Yue Ma's avatar Yue Ma
Browse files

cnss2: Export if DRV is supported through platform capability



Add CNSS_HAS_DRV_SUPPORT to platform capability to indicate if PCIe
DRV is supported or not.

Change-Id: Id114467d060946dda43bb00fe8856cea2c18e738
Signed-off-by: default avatarYue Ma <yuem@codeaurora.org>
parent c77acc02
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+2 −0
Original line number Diff line number Diff line
@@ -206,6 +206,8 @@ int cnss_get_platform_cap(struct device *dev, struct cnss_platform_cap *cap)
	if (cap)
		*cap = plat_priv->cap;

	cnss_pr_dbg("Platform cap_flag is 0x%x\n", cap->cap_flag);

	return 0;
}
EXPORT_SYMBOL(cnss_get_platform_cap);
+4 −0
Original line number Diff line number Diff line
@@ -2210,6 +2210,7 @@ int cnss_pci_unregister_driver_hdlr(struct cnss_pci_data *pci_priv)
static bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
{
	struct pci_dev *root_port = pci_find_pcie_root_port(pci_priv->pci_dev);
	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
	struct device_node *root_of_node;
	bool drv_supported = false;

@@ -2227,6 +2228,9 @@ static bool cnss_pci_is_drv_supported(struct cnss_pci_data *pci_priv)
	cnss_pr_dbg("PCIe DRV is %s\n",
		    drv_supported ? "supported" : "not supported");

	if (drv_supported)
		plat_priv->cap.cap_flag |= CNSS_HAS_DRV_SUPPORT;

	return drv_supported;
}

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ enum cnss_bus_width_type {
enum cnss_platform_cap_flag {
	CNSS_HAS_EXTERNAL_SWREG = 0x01,
	CNSS_HAS_UART_ACCESS = 0x02,
	CNSS_HAS_DRV_SUPPORT = 0x04,
};

struct cnss_platform_cap {