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Commit 4a8e06f7 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/sdma: fix mask in emit_pipeline_sync 



Needs to be a 32 bit mask.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 326aa996

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+1 −1
Original line number Diff line number Diff line
@@ -859,7 +859,7 @@ static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq); /* reference */

	amdgpu_ring_write(ring, 0xfffffff); /* mask */

	amdgpu_ring_write(ring, 0xffffffff); /* mask */

	amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */

}

drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

+1 −1
Original line number Diff line number Diff line
@@ -837,7 +837,7 @@ static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq); /* reference */

	amdgpu_ring_write(ring, 0xfffffff); /* mask */

	amdgpu_ring_write(ring, 0xffffffff); /* mask */

	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |

			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */

}

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1105,7 +1105,7 @@ static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq); /* reference */

	amdgpu_ring_write(ring, 0xfffffff); /* mask */

	amdgpu_ring_write(ring, 0xffffffff); /* mask */

	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |

			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */

}

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

+1 −1
Original line number Diff line number Diff line
@@ -1121,7 +1121,7 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 
	amdgpu_ring_write(ring, addr & 0xfffffffc);

	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);

	amdgpu_ring_write(ring, seq); /* reference */

	amdgpu_ring_write(ring, 0xfffffff); /* mask */

	amdgpu_ring_write(ring, 0xffffffff); /* mask */

	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |

			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */

}