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Commit 4a81fb3f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add secondary clocks for lito"

parents 480f14d7 ad19d8a0

qcom/lito-sde-display.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -421,7 +421,7 @@ 


&dsi_sim_sec_hd_cmd {

	qcom,ulps-enabled;

	qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1";

	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -493,6 +493,7 @@ 
	qcom,mdss-dsi-panel-on-check-value = <0x9c>;

	qcom,mdss-dsi-panel-status-read-length = <1>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
@@ -517,6 +518,7 @@ 
	qcom,mdss-dsi-min-refresh-rate = <48>;

	qcom,mdss-dsi-max-refresh-rate = <60>;

	qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";

	qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";

	qcom,mdss-dsi-display-timings {

		timing@0 {

			qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22