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Commit 49fa4d9b authored by Axel Lin's avatar Axel Lin Committed by Mark Brown
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ASoC: wm8940: Fix setting PLL Output clock division ratio 



According to the datasheet:
The PLL Output clock division ratio is controlled by BIT[5:4] of
WM8940_GPIO register(08h).
Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.

Signed-off-by: default avatarAxel Lin <axel.lin@gmail.com>
Acked-by: default avatarLiam Girdwood <lrg@ti.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 753ddf52

sound/soc/codecs/wm8940.c

+2 −2
Original line number Diff line number Diff line
@@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai, 
		ret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));

		break;

	case WM8940_OPCLKDIV:

		reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;

		ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));

		reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF;

		ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4));

		break;

	}

	return ret;