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Commit 49cf4a4b authored May 10, 2018 by Ingo Molnar

Merge tag 'perf-urgent-for-mingo-4.17-20180507' of...

Merge tag 'perf-urgent-for-mingo-4.17-20180507' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux

 into perf/urgent

Pull perf/urgent fixes from Arnaldo Carvalho de Melo:

. Revert "perf pmu: Fix pmu events parsing rule", as it broke Intel PT
  event description parsing (Arnaldo Carvalho de Melo)

. Sync x86's cpufeatures.h and kvm UAPI headers with the kernel sources,
  suppressing the ABI drift warnings (Arnaldo Carvalho de Melo)

- Remove duplicated entry for westmereep-dp in Intel's mapfile.csv (William Cohen)

- Fix typo in 'perf bench numa' options description (Yisheng Xie)

Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>

parents 75bc37fe 4a35a902

tools/arch/arm/include/uapi/asm/kvm.h

+6 −0

Original line number	Original line	Diff line number	Diff line
	@@ -195,6 +195,12 @@ struct kvm_arch_memory_slot {
	#define KVM_REG_ARM_VFP_FPINST 0x1009		#define KVM_REG_ARM_VFP_FPINST 0x1009
	#define KVM_REG_ARM_VFP_FPINST2 0x100A		#define KVM_REG_ARM_VFP_FPINST2 0x100A

			/* KVM-as-firmware specific pseudo-registers */
			#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
			#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM \| KVM_REG_SIZE_U64 \| \
			KVM_REG_ARM_FW \| ((r) & 0xffff))
			#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)

	/* Device Control API: ARM VGIC */		/* Device Control API: ARM VGIC */
	#define KVM_DEV_ARM_VGIC_GRP_ADDR 0		#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
	#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1		#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1

tools/arch/arm64/include/uapi/asm/kvm.h

+6 −0

Original line number	Original line	Diff line number	Diff line
	@@ -206,6 +206,12 @@ struct kvm_arch_memory_slot {
	#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)		#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
	#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)		#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)

			/* KVM-as-firmware specific pseudo-registers */
			#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
			#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 \| KVM_REG_SIZE_U64 \| \
			KVM_REG_ARM_FW \| ((r) & 0xffff))
			#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)

	/* Device Control API: ARM VGIC */		/* Device Control API: ARM VGIC */
	#define KVM_DEV_ARM_VGIC_GRP_ADDR 0		#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
	#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1		#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1

tools/arch/x86/include/asm/cpufeatures.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -320,6 +320,7 @@
	#define X86_FEATURE_AVX512_VPOPCNTDQ (1632+14) / POPCNT for vectors of DW/QW */		#define X86_FEATURE_AVX512_VPOPCNTDQ (1632+14) / POPCNT for vectors of DW/QW */
	#define X86_FEATURE_LA57 (1632+16) / 5-level page tables */		#define X86_FEATURE_LA57 (1632+16) / 5-level page tables */
	#define X86_FEATURE_RDPID (1632+22) / RDPID instruction */		#define X86_FEATURE_RDPID (1632+22) / RDPID instruction */
			#define X86_FEATURE_CLDEMOTE (1632+25) / CLDEMOTE instruction */

	/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */		/* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
	#define X86_FEATURE_OVERFLOW_RECOV (1732+ 0) / MCA overflow recovery support */		#define X86_FEATURE_OVERFLOW_RECOV (1732+ 0) / MCA overflow recovery support */

tools/include/uapi/linux/kvm.h

+7 −0

Original line number	Original line	Diff line number	Diff line
	@@ -676,6 +676,13 @@ struct kvm_ioeventfd {
	__u8 pad[36];		__u8 pad[36];
	};		};

			#define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0)
			#define KVM_X86_DISABLE_EXITS_HTL (1 << 1)
			#define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2)
			#define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT \| \
			KVM_X86_DISABLE_EXITS_HTL \| \
			KVM_X86_DISABLE_EXITS_PAUSE)

	/* for KVM_ENABLE_CAP */		/* for KVM_ENABLE_CAP */
	struct kvm_enable_cap {		struct kvm_enable_cap {
	/* in */		/* in */

tools/perf/bench/numa.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -175,7 +175,7 @@ static const struct option options[] = {
	OPT_UINTEGER('s', "nr_secs" , &p0.nr_secs, "max number of seconds to run (default: 5 secs)"),		OPT_UINTEGER('s', "nr_secs" , &p0.nr_secs, "max number of seconds to run (default: 5 secs)"),
	OPT_UINTEGER('u', "usleep" , &p0.sleep_usecs, "usecs to sleep per loop iteration"),		OPT_UINTEGER('u', "usleep" , &p0.sleep_usecs, "usecs to sleep per loop iteration"),

	OPT_BOOLEAN('R', "data_reads" , &p0.data_reads, "access the data via writes (can be mixed with -W)"),		OPT_BOOLEAN('R', "data_reads" , &p0.data_reads, "access the data via reads (can be mixed with -W)"),
	OPT_BOOLEAN('W', "data_writes" , &p0.data_writes, "access the data via writes (can be mixed with -R)"),		OPT_BOOLEAN('W', "data_writes" , &p0.data_writes, "access the data via writes (can be mixed with -R)"),
	OPT_BOOLEAN('B', "data_backwards", &p0.data_backwards, "access the data backwards as well"),		OPT_BOOLEAN('B', "data_backwards", &p0.data_backwards, "access the data backwards as well"),
	OPT_BOOLEAN('Z', "data_zero_memset", &p0.data_zero_memset,"access the data via glibc bzero only"),		OPT_BOOLEAN('Z', "data_zero_memset", &p0.data_zero_memset,"access the data via glibc bzero only"),