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Commit 49c98250 authored by Pankaj Gupta's avatar Pankaj Gupta
Browse files

msm: kgsl: Do not enable adreno core feature by default 



Do not enable SP/TP hardware controlled power collapse
feature by default. This feature should be enabled by
defining in gpulist of the target.
Without this fix respective sysfs entry will show
incorrect value.

Change-Id: I78b3cd856dc5b684023bad023ad4c96fd2bdd946
Signed-off-by: default avatarPankaj Gupta <gpankaj@codeaurora.org>
parent a595e17a

drivers/gpu/msm/adreno.c

+1 −2
Original line number Diff line number Diff line
@@ -59,8 +59,7 @@ static struct adreno_device device_3d0 = { 
	.long_ib_detect = 1,

	.input_work = __WORK_INITIALIZER(device_3d0.input_work,

		adreno_input_work),

	.pwrctrl_flag = BIT(ADRENO_SPTP_PC_CTRL) |

		BIT(ADRENO_THROTTLING_CTRL) | BIT(ADRENO_HWCG_CTRL),

	.pwrctrl_flag = BIT(ADRENO_THROTTLING_CTRL) | BIT(ADRENO_HWCG_CTRL),

	.profile.enabled = false,

	.active_list = LIST_HEAD_INIT(device_3d0.active_list),

	.active_list_lock = __SPIN_LOCK_UNLOCKED(device_3d0.active_list_lock),

drivers/gpu/msm/adreno_a5xx.c

+4 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/clk/qcom.h>
@@ -149,6 +149,9 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
	/* Set the GPU busy counter to use for frequency scaling */

	adreno_dev->perfctr_pwr_lo = A5XX_RBBM_PERFCTR_RBBM_0_LO;



	if (ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		set_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);



	/* Check efuse bits for various capabilties */

	a5xx_check_features(adreno_dev);

}

drivers/gpu/msm/adreno_a6xx.c

+3 −0
Original line number Diff line number Diff line
@@ -2325,6 +2325,9 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 
		adreno_dev->perfctr_ifpc_lo =

			A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L;



	if (ADRENO_FEATURE(adreno_dev, ADRENO_SPTP_PC))

		set_bit(ADRENO_SPTP_PC_CTRL, &adreno_dev->pwrctrl_flag);



	/* Check efuse bits for various capabilties */

	a6xx_check_features(adreno_dev);

}