Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 49bc6dea authored by Greg Ungerer's avatar Greg Ungerer
Browse files

m68knommu: limit interrupts supported by ColdFire intc-2 driver



The intc-2 interrupt controller on some ColdFire CPUs has a set range of
interrupts its supports (64 through 128 or 192 depending on model). We
shouldn't be setting this handler for every possible interrupt from 0 to
255. Set more appropriate limits, and this means we can drop the interrupt
number check in the mask and unmask routines.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent 7badfabb
Loading
Loading
Loading
Loading
+25 −33
Original line number Diff line number Diff line
@@ -45,13 +45,10 @@ static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);

static void intc_irq_mask(struct irq_data *d)
{
	unsigned int irq = d->irq;

	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
	unsigned int irq = d->irq - MCFINT_VECBASE;
	unsigned long imraddr;
	u32 val, imrbit;

		irq -= MCFINT_VECBASE;
#ifdef MCFICM_INTC1
	imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
@@ -63,17 +60,13 @@ static void intc_irq_mask(struct irq_data *d)
	val = __raw_readl(imraddr);
	__raw_writel(val | imrbit, imraddr);
}
}

static void intc_irq_unmask(struct irq_data *d)
{
	unsigned int irq = d->irq;

	if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
	unsigned int irq = d->irq - MCFINT_VECBASE;
	unsigned long intaddr, imraddr, icraddr;
	u32 val, imrbit;

		irq -= MCFINT_VECBASE;
#ifdef MCFICM_INTC1
	intaddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
#else
@@ -93,7 +86,6 @@ static void intc_irq_unmask(struct irq_data *d)
	val = __raw_readl(imraddr);
	__raw_writel(val & ~imrbit, imraddr);
}
}

static int intc_irq_set_type(struct irq_data *d, unsigned int type)
{
@@ -119,7 +111,7 @@ void __init init_IRQ(void)
	__raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
#endif

	for (irq = 0; (irq < NR_IRQS); irq++) {
	for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
		set_irq_chip(irq, &intc_irq_chip);
		set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
		set_irq_handler(irq, handle_level_irq);