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Commit 490b8981 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'for-upstream/malidp-fixes' of git://linux-arm.org/linux-ld into drm-fixes 

* 'for-upstream/malidp-fixes' of git://linux-arm.org/linux-ld:
  drm: mali-dp: Fix smart layer not going to composition
  drm: mali-dp: Remove mclk rate management
parents 6ed51175 d1479f61

drivers/gpu/drm/arm/malidp_crtc.c

+1 −2
Original line number Diff line number Diff line
@@ -63,8 +63,7 @@ static void malidp_crtc_enable(struct drm_crtc *crtc) 


	clk_prepare_enable(hwdev->pxlclk);



	/* mclk needs to be set to the same or higher rate than pxlclk */

	clk_set_rate(hwdev->mclk, crtc->state->adjusted_mode.crtc_clock * 1000);

	/* We rely on firmware to set mclk to a sensible level. */

	clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);



	hwdev->modeset(hwdev, &vm);

drivers/gpu/drm/arm/malidp_hw.c

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ static const struct malidp_layer malidp550_layers[] = { 
	{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },

	{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },

	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, 0 },

	{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE },

};



#define MALIDP_DE_DEFAULT_PREFETCH_START	5

drivers/gpu/drm/arm/malidp_planes.c

+16 −2
Original line number Diff line number Diff line
@@ -37,6 +37,8 @@ 
#define   LAYER_V_VAL(x)		(((x) & 0x1fff) << 16)

#define MALIDP_LAYER_COMP_SIZE		0x010

#define MALIDP_LAYER_OFFSET		0x014

#define MALIDP550_LS_ENABLE		0x01c

#define MALIDP550_LS_R1_IN_SIZE		0x020



/*

 * This 4-entry look-up-table is used to determine the full 8-bit alpha value
@@ -242,6 +244,11 @@ static void malidp_de_plane_update(struct drm_plane *plane, 
			LAYER_V_VAL(plane->state->crtc_y),

			mp->layer->base + MALIDP_LAYER_OFFSET);



	if (mp->layer->id == DE_SMART)

		malidp_hw_write(mp->hwdev,

				LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),

				mp->layer->base + MALIDP550_LS_R1_IN_SIZE);



	/* first clear the rotation bits */

	val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);

	val &= ~LAYER_ROT_MASK;
@@ -330,9 +337,16 @@ int malidp_de_planes_init(struct drm_device *drm) 
		plane->hwdev = malidp->dev;

		plane->layer = &map->layers[i];



		/* Skip the features which the SMART layer doesn't have */

		if (id == DE_SMART)

		if (id == DE_SMART) {

			/*

			 * Enable the first rectangle in the SMART layer to be

			 * able to use it as a drm plane.

			 */

			malidp_hw_write(malidp->dev, 1,

					plane->layer->base + MALIDP550_LS_ENABLE);

			/* Skip the features which the SMART layer doesn't have. */

			continue;

		}



		drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags);

		malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,

drivers/gpu/drm/arm/malidp_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ 
/* Stride register offsets relative to Lx_BASE */

#define MALIDP_DE_LG_STRIDE		0x18

#define MALIDP_DE_LV_STRIDE0		0x18

#define MALIDP550_DE_LS_R1_STRIDE	0x28



/* macros to set values into registers */

#define MALIDP_DE_H_FRONTPORCH(x)	(((x) & 0xfff) << 0)