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Commit 48f61314 authored by David Collins's avatar David Collins
Browse files

ARM: dts: msm: enable register retention for GDSC regulators on KONA 



Specify the qcom,retain-regs property for KONA gdsc-regulator
devices so that subsystem retention registers associated with
each GDSC maintain their state when a given GDSC is disabled
and then re-enabled.

Change-Id: If4dedf9a89734d17a528db9f4f7c00c48f13354c
Signed-off-by: default avatarDavid Collins <collinsd@codeaurora.org>
parent ac279b31

arch/arm64/boot/dts/qcom/kona.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -1470,42 +1470,49 @@ 
		compatible = "qcom,gdsc";

		reg = <0x16b004 0x4>;

		regulator-name = "pcie_0_gdsc";

		qcom,retain-regs;

	};



	pcie_1_gdsc: qcom,gdsc@18d004 {

		compatible = "qcom,gdsc";

		reg = <0x18d004 0x4>;

		regulator-name = "pcie_1_gdsc";

		qcom,retain-regs;

	};



	pcie_2_gdsc: qcom,gdsc@106004 {

		compatible = "qcom,gdsc";

		reg = <0x106004 0x4>;

		regulator-name = "pcie_2_gdsc";

		qcom,retain-regs;

	};



	ufs_card_gdsc: qcom,gdsc@175004 {

		compatible = "qcom,gdsc";

		reg = <0x175004 0x4>;

		regulator-name = "ufs_card_gdsc";

		qcom,retain-regs;

	};



	ufs_phy_gdsc: qcom,gdsc@177004 {

		compatible = "qcom,gdsc";

		reg = <0x177004 0x4>;

		regulator-name = "ufs_phy_gdsc";

		qcom,retain-regs;

	};



	usb30_prim_gdsc: qcom,gdsc@10f004 {

		compatible = "qcom,gdsc";

		reg = <0x10f004 0x4>;

		regulator-name = "usb30_prim_gdsc";

		qcom,retain-regs;

	};



	usb30_sec_gdsc: qcom,gdsc@110004 {

		compatible = "qcom,gdsc";

		reg = <0x110004 0x4>;

		regulator-name = "usb30_sec_gdsc";

		qcom,retain-regs;

	};



	hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
@@ -1550,6 +1557,7 @@ 
		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,support-hw-trigger;

		qcom,retain-regs;

	};



	ife_0_gdsc: qcom,gdsc@ad0a004 {
@@ -1560,6 +1568,7 @@ 
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,retain-regs;

	};



	ife_1_gdsc: qcom,gdsc@ad0b004 {
@@ -1570,6 +1579,7 @@ 
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,retain-regs;

	};



	ipe_0_gdsc: qcom,gdsc@ad08004 {
@@ -1581,6 +1591,7 @@ 
		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,support-hw-trigger;

		qcom,retain-regs;

	};



	sbi_gdsc: qcom,gdsc@ad09004 {
@@ -1591,6 +1602,7 @@ 
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,retain-regs;

	};



	titan_top_gdsc: qcom,gdsc@ad0c144 {
@@ -1601,6 +1613,7 @@ 
		clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;

		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,retain-regs;

	};



	/* DISP_CC GDSC */
@@ -1613,6 +1626,7 @@ 
		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,support-hw-trigger;

		qcom,retain-regs;

	};



	/* GPU_CC GDSCs */
@@ -1630,6 +1644,7 @@ 
		qcom,no-status-check-on-disable;

		qcom,clk-dis-wait-val = <8>;

		qcom,gds-timeout = <500>;

		qcom,retain-regs;

	};



	gpu_gx_domain_addr: syscon@3d91508 {
@@ -1651,6 +1666,7 @@ 
		parent-supply = <&VDD_GFX_LEVEL>;

		vdd_parent-supply = <&VDD_GFX_LEVEL>;

		qcom,reset-aon-logic;

		qcom,retain-regs;

	};



	/* NPU GDSC */
@@ -1660,6 +1676,7 @@ 
		regulator-name = "npu_core_gdsc";

		clock-names = "ahb_clk";

		clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;

		qcom,retain-regs;

	};



	qcom,sps {
@@ -1677,6 +1694,7 @@ 
		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,support-hw-trigger;

		qcom,retain-regs;

	};



	mvs0c_gdsc: qcom,gdsc@abf0bf8 {
@@ -1688,6 +1706,7 @@ 
		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,support-hw-trigger;

		qcom,retain-regs;

	};



	mvs1_gdsc: qcom,gdsc@abf0d98 {
@@ -1699,6 +1718,7 @@ 
		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,support-hw-trigger;

		qcom,retain-regs;

	};



	mvs1c_gdsc: qcom,gdsc@abf0c98 {
@@ -1709,6 +1729,7 @@ 
		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

		parent-supply = <&VDD_MMCX_LEVEL>;

		vdd_parent-supply = <&VDD_MMCX_LEVEL>;

		qcom,retain-regs;

	};



	spmi_bus: qcom,spmi@c440000 {