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Commit 488f270d authored by Roger Quadros's avatar Roger Quadros Committed by Tony Lindgren
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ARM: dts: dra7: Fix NAND device nodes



Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.

Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 92e963f5
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+5 −1
Original line number Diff line number Diff line
@@ -741,9 +741,13 @@
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x16>;
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>; /* termcount */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;
+2 −0
Original line number Diff line number Diff line
@@ -1438,6 +1438,8 @@
			gpmc,num-waitpins = <2>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			status = "disabled";
		};

+5 −1
Original line number Diff line number Diff line
@@ -492,13 +492,17 @@
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_default>;
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	ranges = <0 0 0x08000000 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		/* To use NAND, DIP switch SW5 must be set like so:
		 * SW5.1 (NAND_SELn) = ON (LOW)
		 * SW5.9 (GPMC_WPN) = OFF (HIGH)
		 */
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;		/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		ti,nand-ecc-opt = "bch8";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>;