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Commit 4861292f authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bnx2x' 



Yuval Mintz says:

====================
bnx2x: Bug fixes patch series

This series contains several fixes, relating either to SR-IOV flows
or to critical sections protected by the rtnl lock.

Please consider applying these patches to `net'.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents eca42aaf 6ffa39f2

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h

+0 −1
Original line number Diff line number Diff line
@@ -1376,7 +1376,6 @@ enum { 
	BNX2X_SP_RTNL_RX_MODE,

	BNX2X_SP_RTNL_HYPERVISOR_VLAN,

	BNX2X_SP_RTNL_TX_STOP,

	BNX2X_SP_RTNL_TX_RESUME,

};



struct bnx2x_prev_path_list {

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c

+4 −0
Original line number Diff line number Diff line
@@ -2959,6 +2959,10 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link) 


	bp->port.pmf = 0;



	/* clear pending work in rtnl task */

	bp->sp_rtnl_state = 0;

	smp_mb();



	/* Free SKBs, SGEs, TPA pool and driver internals */

	bnx2x_free_skbs(bp);

	if (CNIC_LOADED(bp))

drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c

+0 −5
Original line number Diff line number Diff line
@@ -778,11 +778,6 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state) 


		/* ets may affect cmng configuration: reinit it in hw */

		bnx2x_set_local_cmng(bp);



		set_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state);



		schedule_delayed_work(&bp->sp_rtnl_task, 0);



		return;

	case BNX2X_DCBX_STATE_TX_RELEASED:

		DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_TX_RELEASED\n");

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+12 −5
Original line number Diff line number Diff line
@@ -577,7 +577,9 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 
	rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));

	if (rc) {

		BNX2X_ERR("DMAE returned failure %d\n", rc);

#ifdef BNX2X_STOP_ON_ERROR

		bnx2x_panic();

#endif

	}

}
@@ -614,7 +616,9 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) 
	rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));

	if (rc) {

		BNX2X_ERR("DMAE returned failure %d\n", rc);

#ifdef BNX2X_STOP_ON_ERROR

		bnx2x_panic();

#endif

	}

}
@@ -5231,18 +5235,18 @@ static void bnx2x_eq_int(struct bnx2x *bp) 


		case EVENT_RING_OPCODE_STOP_TRAFFIC:

			DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");

			bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);

			if (f_obj->complete_cmd(bp, f_obj,

						BNX2X_F_CMD_TX_STOP))

				break;

			bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);

			goto next_spqe;



		case EVENT_RING_OPCODE_START_TRAFFIC:

			DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");

			bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);

			if (f_obj->complete_cmd(bp, f_obj,

						BNX2X_F_CMD_TX_START))

				break;

			bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);

			goto next_spqe;



		case EVENT_RING_OPCODE_FUNCTION_UPDATE:
@@ -9352,6 +9356,10 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global) 
	bnx2x_process_kill_chip_reset(bp, global);

	barrier();



	/* clear errors in PGB */

	if (!CHIP_IS_E1x(bp))

		REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);



	/* Recover after reset: */

	/* MCP */

	if (global && bnx2x_reset_mcp_comp(bp, val))
@@ -9706,11 +9714,10 @@ static void bnx2x_sp_rtnl_task(struct work_struct *work) 
			       &bp->sp_rtnl_state))

		bnx2x_pf_set_vfs_vlan(bp);



	if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state))

	if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {

		bnx2x_dcbx_stop_hw_tx(bp);



	if (test_and_clear_bit(BNX2X_SP_RTNL_TX_RESUME, &bp->sp_rtnl_state))

		bnx2x_dcbx_resume_hw_tx(bp);

	}



	/* work which needs rtnl lock not-taken (as it takes the lock itself and

	 * can be called from other contexts as well)

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+11 −0
Original line number Diff line number Diff line
@@ -2864,6 +2864,17 @@ 
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ		 0x9430

#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE		 0x9434

#define PGLUE_B_REG_INTERNAL_VFID_ENABLE			 0x9438

/* [W 7] Writing 1 to each bit in this register clears a corresponding error

 * details register and enables logging new error details. Bit 0 - clears

 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears

 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS

 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32

 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -

 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears

 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6

 * - clears TCPL_IN_TWO_RCBS_DETAILS. */

#define PGLUE_B_REG_LATCHED_ERRORS_CLR				 0x943c



/* [R 9] Interrupt register #0 read */

#define PGLUE_B_REG_PGLUE_B_INT_STS				 0x9298

/* [RC 9] Interrupt register #0 read clear */