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Commit 484d0e5c authored by Andy Lutomirski's avatar Andy Lutomirski Committed by Thomas Gleixner
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x86/microcode/intel: Replace sync_core() with native_cpuid() 



The Intel microcode driver is using sync_core() to mean "do CPUID
with EAX=1".  I want to rework sync_core(), but first the Intel
microcode driver needs to stop depending on its current behavior.

Reported-by: default avatarHenrique de Moraes Holschuh <hmh@hmh.eng.br>
Signed-off-by: default avatarAndy Lutomirski <luto@kernel.org>
Acked-by: default avatarBorislav Petkov <bp@alien8.de>
Cc: Juergen Gross <jgross@suse.com>
Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Matthew Whitehead <tedheadster@gmail.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: xen-devel <Xen-devel@lists.xen.org>
Link: http://lkml.kernel.org/r/535a025bb91fed1a019c5412b036337ad239e5bb.1481307769.git.luto@kernel.org


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 426d1aff

arch/x86/kernel/cpu/microcode/intel.c

+23 −3
Original line number Diff line number Diff line
@@ -368,6 +368,26 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) 
	return patch;

}



static void cpuid_1(void)

{

	/*

	 * According to the Intel SDM, Volume 3, 9.11.7:

	 *

	 *   CPUID returns a value in a model specific register in

	 *   addition to its usual register return values. The

	 *   semantics of CPUID cause it to deposit an update ID value

	 *   in the 64-bit model-specific register at address 08BH

	 *   (IA32_BIOS_SIGN_ID). If no update is present in the

	 *   processor, the value in the MSR remains unmodified.

	 *

	 * Use native_cpuid -- this code runs very early and we don't

	 * want to mess with paravirt.

	 */

	unsigned int eax = 1, ebx, ecx = 0, edx;



	native_cpuid(&eax, &ebx, &ecx, &edx);

}



static int collect_cpu_info_early(struct ucode_cpu_info *uci)

{

	unsigned int val[2];
@@ -393,7 +413,7 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci) 
	native_wrmsrl(MSR_IA32_UCODE_REV, 0);



	/* As documented in the SDM: Do a CPUID 1 here */

	sync_core();

	cpuid_1();



	/* get the current revision from MSR 0x8B */

	native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
@@ -593,7 +613,7 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) 
	native_wrmsrl(MSR_IA32_UCODE_REV, 0);



	/* As documented in the SDM: Do a CPUID 1 here */

	sync_core();

	cpuid_1();



	/* get the current revision from MSR 0x8B */

	native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
@@ -805,7 +825,7 @@ static int apply_microcode_intel(int cpu) 
	wrmsrl(MSR_IA32_UCODE_REV, 0);



	/* As documented in the SDM: Do a CPUID 1 here */

	sync_core();

	cpuid_1();



	/* get the current revision from MSR 0x8B */

	rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);