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Commit 4827c547 authored by Oscar Mateo's avatar Oscar Mateo Committed by Chris Wilson
Browse files

drm/i915: Transform WaDisableGafsUnitClkGating into a simple reg write 



GEN7_UCGCTL4 does not live in the context.

v2: Missing parenthesis

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Reviewed-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1504798809-5653-4-git-send-email-oscar.mateo@intel.com


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent b27f5901

drivers/gpu/drm/i915/intel_engine_cs.c

+6 −3
Original line number Diff line number Diff line
@@ -981,7 +981,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) 
				   GEN9_GAPS_TSV_CREDIT_DISABLE));



	/* WaDisableGafsUnitClkGating:skl */

	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |

				  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));



	/* WaInPlaceDecompressionHang:skl */

	if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER))
@@ -1143,7 +1144,8 @@ static int kbl_init_workarounds(struct intel_engine_cs *engine) 
				  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);



	/* WaDisableGafsUnitClkGating:kbl */

	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |

				  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));



	/* WaDisableSbeCacheDispatchPortSharing:kbl */

	WA_SET_BIT_MASKED(
@@ -1197,7 +1199,8 @@ static int cfl_init_workarounds(struct intel_engine_cs *engine) 
			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);



	/* WaDisableGafsUnitClkGating:cfl */

	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);

	I915_WRITE(GEN7_UCGCTL4, (I915_READ(GEN7_UCGCTL4) |

				  GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE));



	/* WaDisableSbeCacheDispatchPortSharing:cfl */

	WA_SET_BIT_MASKED(