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Commit 475549fa authored by Lennert Buytenhek's avatar Lennert Buytenhek Committed by Russell King
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[ARM] 3831/1: iop3xx: factor out common register defines 



Factor out the register defines for a number of other peripherals
common to the iop32x and iop33x.

Signed-off-by: default avatarLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent c680b77e

include/asm-arm/arch-iop32x/iop321.h

+0 −132
Original line number Diff line number Diff line
@@ -37,102 +37,13 @@ 


/* Messaging Unit 0x00000300 through 0x000003FF */



/* Reserved 0x00000300 through 0x0000030c */

#define IOP321_IMR0       (volatile u32 *)IOP321_REG_ADDR(0x00000310)

#define IOP321_IMR1       (volatile u32 *)IOP321_REG_ADDR(0x00000314)

#define IOP321_OMR0       (volatile u32 *)IOP321_REG_ADDR(0x00000318)

#define IOP321_OMR1       (volatile u32 *)IOP321_REG_ADDR(0x0000031C)

#define IOP321_IDR        (volatile u32 *)IOP321_REG_ADDR(0x00000320)

#define IOP321_IISR       (volatile u32 *)IOP321_REG_ADDR(0x00000324)

#define IOP321_IIMR       (volatile u32 *)IOP321_REG_ADDR(0x00000328)

#define IOP321_ODR        (volatile u32 *)IOP321_REG_ADDR(0x0000032C)

#define IOP321_OISR       (volatile u32 *)IOP321_REG_ADDR(0x00000330)

#define IOP321_OIMR       (volatile u32 *)IOP321_REG_ADDR(0x00000334)

/* Reserved 0x00000338 through 0x0000034F */

#define IOP321_MUCR       (volatile u32 *)IOP321_REG_ADDR(0x00000350)

#define IOP321_QBAR       (volatile u32 *)IOP321_REG_ADDR(0x00000354)

/* Reserved 0x00000358 through 0x0000035C */

#define IOP321_IFHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000360)

#define IOP321_IFTPR      (volatile u32 *)IOP321_REG_ADDR(0x00000364)

#define IOP321_IPHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000368)

#define IOP321_IPTPR      (volatile u32 *)IOP321_REG_ADDR(0x0000036C)

#define IOP321_OFHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000370)

#define IOP321_OFTPR      (volatile u32 *)IOP321_REG_ADDR(0x00000374)

#define IOP321_OPHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000378)

#define IOP321_OPTPR      (volatile u32 *)IOP321_REG_ADDR(0x0000037C)

#define IOP321_IAR        (volatile u32 *)IOP321_REG_ADDR(0x00000380)



#define IOP321_IIxR_MASK	0x7f /* masks all */

#define IOP321_IIxR_IRI		0x40 /* RC Index Register Interrupt */

#define IOP321_IIxR_OFQF	0x20 /* RC Output Free Q Full (ERROR) */

#define IOP321_IIxR_ipq		0x10 /* RC Inbound Post Q (post) */

#define IOP321_IIxR_ERRDI	0x08 /* RO Error Doorbell Interrupt */

#define IOP321_IIxR_IDI		0x04 /* RO Inbound Doorbell Interrupt */

#define IOP321_IIxR_IM1		0x02 /* RC Inbound Message 1 Interrupt */

#define IOP321_IIxR_IM0		0x01 /* RC Inbound Message 0 Interrupt */



/* Reserved 0x00000384 through 0x000003FF */



/* DMA Controller 0x00000400 through 0x000004FF */

#define IOP321_DMA0_CCR   (volatile u32 *)IOP321_REG_ADDR(0x00000400)

#define IOP321_DMA0_CSR   (volatile u32 *)IOP321_REG_ADDR(0x00000404)

#define IOP321_DMA0_DAR   (volatile u32 *)IOP321_REG_ADDR(0x0000040C)

#define IOP321_DMA0_NDAR  (volatile u32 *)IOP321_REG_ADDR(0x00000410)

#define IOP321_DMA0_PADR  (volatile u32 *)IOP321_REG_ADDR(0x00000414)

#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)

#define IOP321_DMA0_LADR  (volatile u32 *)IOP321_REG_ADDR(0X0000041C)

#define IOP321_DMA0_BCR   (volatile u32 *)IOP321_REG_ADDR(0x00000420)

#define IOP321_DMA0_DCR   (volatile u32 *)IOP321_REG_ADDR(0x00000424)

/* Reserved 0x00000428 through 0x0000043C */

#define IOP321_DMA1_CCR   (volatile u32 *)IOP321_REG_ADDR(0x00000440)

#define IOP321_DMA1_CSR   (volatile u32 *)IOP321_REG_ADDR(0x00000444)

#define IOP321_DMA1_DAR   (volatile u32 *)IOP321_REG_ADDR(0x0000044C)

#define IOP321_DMA1_NDAR  (volatile u32 *)IOP321_REG_ADDR(0x00000450)

#define IOP321_DMA1_PADR  (volatile u32 *)IOP321_REG_ADDR(0x00000454)

#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)

#define IOP321_DMA1_LADR  (volatile u32 *)IOP321_REG_ADDR(0x0000045C)

#define IOP321_DMA1_BCR   (volatile u32 *)IOP321_REG_ADDR(0x00000460)

#define IOP321_DMA1_DCR   (volatile u32 *)IOP321_REG_ADDR(0x00000464)

/* Reserved 0x00000468 through 0x000004FF */



/* Memory controller 0x00000500 through 0x0005FF */



/* Peripheral bus interface unit 0x00000680 through 0x0006FF */

#define IOP321_PBCR       (volatile u32 *)IOP321_REG_ADDR(0x00000680)

#define IOP321_PBISR      (volatile u32 *)IOP321_REG_ADDR(0x00000684)

#define IOP321_PBBAR0     (volatile u32 *)IOP321_REG_ADDR(0x00000688)

#define IOP321_PBLR0      (volatile u32 *)IOP321_REG_ADDR(0x0000068C)

#define IOP321_PBBAR1     (volatile u32 *)IOP321_REG_ADDR(0x00000690)

#define IOP321_PBLR1      (volatile u32 *)IOP321_REG_ADDR(0x00000694)

#define IOP321_PBBAR2     (volatile u32 *)IOP321_REG_ADDR(0x00000698)

#define IOP321_PBLR2      (volatile u32 *)IOP321_REG_ADDR(0x0000069C)

#define IOP321_PBBAR3     (volatile u32 *)IOP321_REG_ADDR(0x000006A0)

#define IOP321_PBLR3      (volatile u32 *)IOP321_REG_ADDR(0x000006A4)

#define IOP321_PBBAR4     (volatile u32 *)IOP321_REG_ADDR(0x000006A8)

#define IOP321_PBLR4      (volatile u32 *)IOP321_REG_ADDR(0x000006AC)

#define IOP321_PBBAR5     (volatile u32 *)IOP321_REG_ADDR(0x000006B0)

#define IOP321_PBLR5      (volatile u32 *)IOP321_REG_ADDR(0x000006B4)

#define IOP321_PBDSCR     (volatile u32 *)IOP321_REG_ADDR(0x000006B8)

/* Reserved 0x000006BC */

#define IOP321_PMBR0      (volatile u32 *)IOP321_REG_ADDR(0x000006C0)

/* Reserved 0x000006C4 through 0x000006DC */

#define IOP321_PMBR1      (volatile u32 *)IOP321_REG_ADDR(0x000006E0)

#define IOP321_PMBR2      (volatile u32 *)IOP321_REG_ADDR(0x000006E4)



#define IOP321_PBCR_EN    0x1



#define IOP321_PBISR_BOOR_ERR 0x1



/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */

#define IOP321_GTMR	(volatile u32 *)IOP321_REG_ADDR(0x00000700)

#define IOP321_ESR	(volatile u32 *)IOP321_REG_ADDR(0x00000704)

#define IOP321_EMISR	(volatile u32 *)IOP321_REG_ADDR(0x00000708)

/* reserved 0x00000070c */

#define IOP321_GTSR	(volatile u32 *)IOP321_REG_ADDR(0x00000710)

/* PERC0 DOESN'T EXIST - index from 1! */

#define IOP321_PERCR0	(volatile u32 *)IOP321_REG_ADDR(0x00000710)



#define IOP321_GTMR_NGCE	0x04 /* (Not) Global Counter Enable */



/* Internal arbitration unit 0x00000780 through 0x0007BF */

#define IOP321_IACR	(volatile u32 *)IOP321_REG_ADDR(0x00000780)
@@ -151,49 +62,6 @@ 
#define IOP321_FINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007DC)



/* Application accelerator unit 0x00000800 - 0x000008FF */

#define IOP321_AAU_ACR     (volatile u32 *)IOP321_REG_ADDR(0x00000800)

#define IOP321_AAU_ASR     (volatile u32 *)IOP321_REG_ADDR(0x00000804)

#define IOP321_AAU_ADAR    (volatile u32 *)IOP321_REG_ADDR(0x00000808)

#define IOP321_AAU_ANDAR   (volatile u32 *)IOP321_REG_ADDR(0x0000080C)

#define IOP321_AAU_SAR1    (volatile u32 *)IOP321_REG_ADDR(0x00000810)

#define IOP321_AAU_SAR2    (volatile u32 *)IOP321_REG_ADDR(0x00000814)

#define IOP321_AAU_SAR3    (volatile u32 *)IOP321_REG_ADDR(0x00000818)

#define IOP321_AAU_SAR4    (volatile u32 *)IOP321_REG_ADDR(0x0000081C)

#define IOP321_AAU_SAR5    (volatile u32 *)IOP321_REG_ADDR(0x0000082C)

#define IOP321_AAU_SAR6    (volatile u32 *)IOP321_REG_ADDR(0x00000830)

#define IOP321_AAU_SAR7    (volatile u32 *)IOP321_REG_ADDR(0x00000834)

#define IOP321_AAU_SAR8    (volatile u32 *)IOP321_REG_ADDR(0x00000838)

#define IOP321_AAU_SAR9    (volatile u32 *)IOP321_REG_ADDR(0x00000840)

#define IOP321_AAU_SAR10   (volatile u32 *)IOP321_REG_ADDR(0x00000844)

#define IOP321_AAU_SAR11   (volatile u32 *)IOP321_REG_ADDR(0x00000848)

#define IOP321_AAU_SAR12   (volatile u32 *)IOP321_REG_ADDR(0x0000084C)

#define IOP321_AAU_SAR13   (volatile u32 *)IOP321_REG_ADDR(0x00000850)

#define IOP321_AAU_SAR14   (volatile u32 *)IOP321_REG_ADDR(0x00000854)

#define IOP321_AAU_SAR15   (volatile u32 *)IOP321_REG_ADDR(0x00000858)

#define IOP321_AAU_SAR16   (volatile u32 *)IOP321_REG_ADDR(0x0000085C)

#define IOP321_AAU_SAR17   (volatile u32 *)IOP321_REG_ADDR(0x00000864)

#define IOP321_AAU_SAR18   (volatile u32 *)IOP321_REG_ADDR(0x00000868)

#define IOP321_AAU_SAR19   (volatile u32 *)IOP321_REG_ADDR(0x0000086C)

#define IOP321_AAU_SAR20   (volatile u32 *)IOP321_REG_ADDR(0x00000870)

#define IOP321_AAU_SAR21   (volatile u32 *)IOP321_REG_ADDR(0x00000874)

#define IOP321_AAU_SAR22   (volatile u32 *)IOP321_REG_ADDR(0x00000878)

#define IOP321_AAU_SAR23   (volatile u32 *)IOP321_REG_ADDR(0x0000087C)

#define IOP321_AAU_SAR24   (volatile u32 *)IOP321_REG_ADDR(0x00000880)

#define IOP321_AAU_SAR25   (volatile u32 *)IOP321_REG_ADDR(0x00000888)

#define IOP321_AAU_SAR26   (volatile u32 *)IOP321_REG_ADDR(0x0000088C)

#define IOP321_AAU_SAR27   (volatile u32 *)IOP321_REG_ADDR(0x00000890)

#define IOP321_AAU_SAR28   (volatile u32 *)IOP321_REG_ADDR(0x00000894)

#define IOP321_AAU_SAR29   (volatile u32 *)IOP321_REG_ADDR(0x00000898)

#define IOP321_AAU_SAR30   (volatile u32 *)IOP321_REG_ADDR(0x0000089C)

#define IOP321_AAU_SAR31   (volatile u32 *)IOP321_REG_ADDR(0x000008A0)

#define IOP321_AAU_SAR32   (volatile u32 *)IOP321_REG_ADDR(0x000008A4)

#define IOP321_AAU_DAR     (volatile u32 *)IOP321_REG_ADDR(0x00000820)

#define IOP321_AAU_ABCR    (volatile u32 *)IOP321_REG_ADDR(0x00000824)

#define IOP321_AAU_ADCR    (volatile u32 *)IOP321_REG_ADDR(0x00000828)

#define IOP321_AAU_EDCR0   (volatile u32 *)IOP321_REG_ADDR(0x0000083c)

#define IOP321_AAU_EDCR1   (volatile u32 *)IOP321_REG_ADDR(0x00000860)

#define IOP321_AAU_EDCR2   (volatile u32 *)IOP321_REG_ADDR(0x00000884)





/* SSP serial port unit 0x00001600 - 0x0000167F */

/* I2C bus interface unit 0x00001680 - 0x000016FF */

include/asm-arm/arch-iop33x/iop331.h

+0 −115
Original line number Diff line number Diff line
@@ -36,83 +36,11 @@ 


/* Messaging Unit 0x00000300 through 0x000003FF */



/* Reserved 0x00000300 through 0x0000030c */

#define IOP331_IMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000310)

#define IOP331_IMR1       (volatile u32 *)IOP331_REG_ADDR(0x00000314)

#define IOP331_OMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000318)

#define IOP331_OMR1       (volatile u32 *)IOP331_REG_ADDR(0x0000031C)

#define IOP331_IDR        (volatile u32 *)IOP331_REG_ADDR(0x00000320)

#define IOP331_IISR       (volatile u32 *)IOP331_REG_ADDR(0x00000324)

#define IOP331_IIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000328)

#define IOP331_ODR        (volatile u32 *)IOP331_REG_ADDR(0x0000032C)

#define IOP331_OISR       (volatile u32 *)IOP331_REG_ADDR(0x00000330)

#define IOP331_OIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000334)

/* Reserved 0x00000338 through 0x0000034F */

#define IOP331_MUCR       (volatile u32 *)IOP331_REG_ADDR(0x00000350)

#define IOP331_QBAR       (volatile u32 *)IOP331_REG_ADDR(0x00000354)

/* Reserved 0x00000358 through 0x0000035C */

#define IOP331_IFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000360)

#define IOP331_IFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000364)

#define IOP331_IPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000368)

#define IOP331_IPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000036C)

#define IOP331_OFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000370)

#define IOP331_OFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000374)

#define IOP331_OPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000378)

#define IOP331_OPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000037C)

#define IOP331_IAR        (volatile u32 *)IOP331_REG_ADDR(0x00000380)

/* Reserved 0x00000384 through 0x000003FF */



/* DMA Controller 0x00000400 through 0x000004FF */

#define IOP331_DMA0_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000400)

#define IOP331_DMA0_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000404)

#define IOP331_DMA0_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000040C)

#define IOP331_DMA0_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000410)

#define IOP331_DMA0_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000414)

#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)

#define IOP331_DMA0_LADR  (volatile u32 *)IOP331_REG_ADDR(0X0000041C)

#define IOP331_DMA0_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000420)

#define IOP331_DMA0_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000424)

/* Reserved 0x00000428 through 0x0000043C */

#define IOP331_DMA1_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000440)

#define IOP331_DMA1_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000444)

#define IOP331_DMA1_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000044C)

#define IOP331_DMA1_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000450)

#define IOP331_DMA1_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000454)

#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)

#define IOP331_DMA1_LADR  (volatile u32 *)IOP331_REG_ADDR(0x0000045C)

#define IOP331_DMA1_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000460)

#define IOP331_DMA1_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000464)

/* Reserved 0x00000468 through 0x000004FF */



/* Memory controller 0x00000500 through 0x0005FF */



/* Peripheral bus interface unit 0x00000680 through 0x0006FF */

#define IOP331_PBCR       (volatile u32 *)IOP331_REG_ADDR(0x00000680)

#define IOP331_PBISR      (volatile u32 *)IOP331_REG_ADDR(0x00000684)

#define IOP331_PBBAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000688)

#define IOP331_PBLR0      (volatile u32 *)IOP331_REG_ADDR(0x0000068C)

#define IOP331_PBBAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000690)

#define IOP331_PBLR1      (volatile u32 *)IOP331_REG_ADDR(0x00000694)

#define IOP331_PBBAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000698)

#define IOP331_PBLR2      (volatile u32 *)IOP331_REG_ADDR(0x0000069C)

#define IOP331_PBBAR3     (volatile u32 *)IOP331_REG_ADDR(0x000006A0)

#define IOP331_PBLR3      (volatile u32 *)IOP331_REG_ADDR(0x000006A4)

#define IOP331_PBBAR4     (volatile u32 *)IOP331_REG_ADDR(0x000006A8)

#define IOP331_PBLR4      (volatile u32 *)IOP331_REG_ADDR(0x000006AC)

#define IOP331_PBBAR5     (volatile u32 *)IOP331_REG_ADDR(0x000006B0)

#define IOP331_PBLR5      (volatile u32 *)IOP331_REG_ADDR(0x000006B4)

#define IOP331_PBDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000006B8)

/* Reserved 0x000006BC */

#define IOP331_PMBR0      (volatile u32 *)IOP331_REG_ADDR(0x000006C0)

/* Reserved 0x000006C4 through 0x000006DC */

#define IOP331_PMBR1      (volatile u32 *)IOP331_REG_ADDR(0x000006E0)

#define IOP331_PMBR2      (volatile u32 *)IOP331_REG_ADDR(0x000006E4)



#define IOP331_PBCR_EN    0x1



#define IOP331_PBISR_BOOR_ERR 0x1







/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */

/* Internal arbitration unit 0x00000780 through 0x0007BF */
@@ -137,49 +65,6 @@ 




/* Application accelerator unit 0x00000800 - 0x000008FF */

#define IOP331_AAU_ACR     (volatile u32 *)IOP331_REG_ADDR(0x00000800)

#define IOP331_AAU_ASR     (volatile u32 *)IOP331_REG_ADDR(0x00000804)

#define IOP331_AAU_ADAR    (volatile u32 *)IOP331_REG_ADDR(0x00000808)

#define IOP331_AAU_ANDAR   (volatile u32 *)IOP331_REG_ADDR(0x0000080C)

#define IOP331_AAU_SAR1    (volatile u32 *)IOP331_REG_ADDR(0x00000810)

#define IOP331_AAU_SAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000814)

#define IOP331_AAU_SAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000818)

#define IOP331_AAU_SAR4    (volatile u32 *)IOP331_REG_ADDR(0x0000081C)

#define IOP331_AAU_SAR5    (volatile u32 *)IOP331_REG_ADDR(0x0000082C)

#define IOP331_AAU_SAR6    (volatile u32 *)IOP331_REG_ADDR(0x00000830)

#define IOP331_AAU_SAR7    (volatile u32 *)IOP331_REG_ADDR(0x00000834)

#define IOP331_AAU_SAR8    (volatile u32 *)IOP331_REG_ADDR(0x00000838)

#define IOP331_AAU_SAR9    (volatile u32 *)IOP331_REG_ADDR(0x00000840)

#define IOP331_AAU_SAR10   (volatile u32 *)IOP331_REG_ADDR(0x00000844)

#define IOP331_AAU_SAR11   (volatile u32 *)IOP331_REG_ADDR(0x00000848)

#define IOP331_AAU_SAR12   (volatile u32 *)IOP331_REG_ADDR(0x0000084C)

#define IOP331_AAU_SAR13   (volatile u32 *)IOP331_REG_ADDR(0x00000850)

#define IOP331_AAU_SAR14   (volatile u32 *)IOP331_REG_ADDR(0x00000854)

#define IOP331_AAU_SAR15   (volatile u32 *)IOP331_REG_ADDR(0x00000858)

#define IOP331_AAU_SAR16   (volatile u32 *)IOP331_REG_ADDR(0x0000085C)

#define IOP331_AAU_SAR17   (volatile u32 *)IOP331_REG_ADDR(0x00000864)

#define IOP331_AAU_SAR18   (volatile u32 *)IOP331_REG_ADDR(0x00000868)

#define IOP331_AAU_SAR19   (volatile u32 *)IOP331_REG_ADDR(0x0000086C)

#define IOP331_AAU_SAR20   (volatile u32 *)IOP331_REG_ADDR(0x00000870)

#define IOP331_AAU_SAR21   (volatile u32 *)IOP331_REG_ADDR(0x00000874)

#define IOP331_AAU_SAR22   (volatile u32 *)IOP331_REG_ADDR(0x00000878)

#define IOP331_AAU_SAR23   (volatile u32 *)IOP331_REG_ADDR(0x0000087C)

#define IOP331_AAU_SAR24   (volatile u32 *)IOP331_REG_ADDR(0x00000880)

#define IOP331_AAU_SAR25   (volatile u32 *)IOP331_REG_ADDR(0x00000888)

#define IOP331_AAU_SAR26   (volatile u32 *)IOP331_REG_ADDR(0x0000088C)

#define IOP331_AAU_SAR27   (volatile u32 *)IOP331_REG_ADDR(0x00000890)

#define IOP331_AAU_SAR28   (volatile u32 *)IOP331_REG_ADDR(0x00000894)

#define IOP331_AAU_SAR29   (volatile u32 *)IOP331_REG_ADDR(0x00000898)

#define IOP331_AAU_SAR30   (volatile u32 *)IOP331_REG_ADDR(0x0000089C)

#define IOP331_AAU_SAR31   (volatile u32 *)IOP331_REG_ADDR(0x000008A0)

#define IOP331_AAU_SAR32   (volatile u32 *)IOP331_REG_ADDR(0x000008A4)

#define IOP331_AAU_DAR     (volatile u32 *)IOP331_REG_ADDR(0x00000820)

#define IOP331_AAU_ABCR    (volatile u32 *)IOP331_REG_ADDR(0x00000824)

#define IOP331_AAU_ADCR    (volatile u32 *)IOP331_REG_ADDR(0x00000828)

#define IOP331_AAU_EDCR0   (volatile u32 *)IOP331_REG_ADDR(0x0000083c)

#define IOP331_AAU_EDCR1   (volatile u32 *)IOP331_REG_ADDR(0x00000860)

#define IOP331_AAU_EDCR2   (volatile u32 *)IOP331_REG_ADDR(0x00000884)





#define IOP331_SPDSCR	  (volatile u32 *)IOP331_REG_ADDR(0x000015C0)

#define IOP331_PPDSCR	  (volatile u32 *)IOP331_REG_ADDR(0x000015C8)

include/asm-arm/hardware/iop3xx.h

+114 −0
Original line number Diff line number Diff line
@@ -97,6 +97,76 @@ extern void gpio_line_set(int line, int value); 
#define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)

#define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)



/* Messaging Unit  */

#define IOP3XX_IMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0310)

#define IOP3XX_IMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0314)

#define IOP3XX_OMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0318)

#define IOP3XX_OMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x031c)

#define IOP3XX_IDR		(volatile u32 *)IOP3XX_REG_ADDR(0x0320)

#define IOP3XX_IISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0324)

#define IOP3XX_IIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0328)

#define IOP3XX_ODR		(volatile u32 *)IOP3XX_REG_ADDR(0x032c)

#define IOP3XX_OISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0330)

#define IOP3XX_OIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0334)

#define IOP3XX_MUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0350)

#define IOP3XX_QBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0354)

#define IOP3XX_IFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0360)

#define IOP3XX_IFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0364)

#define IOP3XX_IPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0368)

#define IOP3XX_IPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x036c)

#define IOP3XX_OFHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0370)

#define IOP3XX_OFTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0374)

#define IOP3XX_OPHPR		(volatile u32 *)IOP3XX_REG_ADDR(0x0378)

#define IOP3XX_OPTPR		(volatile u32 *)IOP3XX_REG_ADDR(0x037c)

#define IOP3XX_IAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0380)



/* DMA Controller  */

#define IOP3XX_DMA0_CCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0400)

#define IOP3XX_DMA0_CSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0404)

#define IOP3XX_DMA0_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x040c)

#define IOP3XX_DMA0_NDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x0410)

#define IOP3XX_DMA0_PADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0414)

#define IOP3XX_DMA0_PUADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0418)

#define IOP3XX_DMA0_LADR	(volatile u32 *)IOP3XX_REG_ADDR(0x041c)

#define IOP3XX_DMA0_BCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0420)

#define IOP3XX_DMA0_DCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0424)

#define IOP3XX_DMA1_CCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0440)

#define IOP3XX_DMA1_CSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0444)

#define IOP3XX_DMA1_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x044c)

#define IOP3XX_DMA1_NDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x0450)

#define IOP3XX_DMA1_PADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0454)

#define IOP3XX_DMA1_PUADR	(volatile u32 *)IOP3XX_REG_ADDR(0x0458)

#define IOP3XX_DMA1_LADR	(volatile u32 *)IOP3XX_REG_ADDR(0x045c)

#define IOP3XX_DMA1_BCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0460)

#define IOP3XX_DMA1_DCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0464)



/* Peripheral bus interface  */

#define IOP3XX_PBCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0680)

#define IOP3XX_PBISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0684)

#define IOP3XX_PBBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0688)

#define IOP3XX_PBLR0		(volatile u32 *)IOP3XX_REG_ADDR(0x068c)

#define IOP3XX_PBBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0690)

#define IOP3XX_PBLR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0694)

#define IOP3XX_PBBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0698)

#define IOP3XX_PBLR2		(volatile u32 *)IOP3XX_REG_ADDR(0x069c)

#define IOP3XX_PBBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a0)

#define IOP3XX_PBLR3		(volatile u32 *)IOP3XX_REG_ADDR(0x06a4)

#define IOP3XX_PBBAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06a8)

#define IOP3XX_PBLR4		(volatile u32 *)IOP3XX_REG_ADDR(0x06ac)

#define IOP3XX_PBBAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b0)

#define IOP3XX_PBLR5		(volatile u32 *)IOP3XX_REG_ADDR(0x06b4)

#define IOP3XX_PMBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x06c0)

#define IOP3XX_PMBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x06e0)

#define IOP3XX_PMBR2		(volatile u32 *)IOP3XX_REG_ADDR(0x06e4)



/* Peripheral performance monitoring unit  */

#define IOP3XX_GTMR		(volatile u32 *)IOP3XX_REG_ADDR(0x0700)

#define IOP3XX_ESR		(volatile u32 *)IOP3XX_REG_ADDR(0x0704)

#define IOP3XX_EMISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0708)

#define IOP3XX_GTSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)

/* PERCR0 DOESN'T EXIST - index from 1! */

#define IOP3XX_PERCR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0710)



/* General Purpose I/O  */

#define IOP3XX_GPOE		(volatile u32 *)IOP3XX_GPIO_REG(0x0004)

#define IOP3XX_GPID		(volatile u32 *)IOP3XX_GPIO_REG(0x0008)
@@ -120,6 +190,50 @@ extern void gpio_line_set(int line, int value); 
#define IOP3XX_TMR_RATIO_8_1	0x20

#define IOP3XX_TMR_RATIO_16_1	0x30



/* Application accelerator unit  */

#define IOP3XX_AAU_ACR		(volatile u32 *)IOP3XX_REG_ADDR(0x0800)

#define IOP3XX_AAU_ASR		(volatile u32 *)IOP3XX_REG_ADDR(0x0804)

#define IOP3XX_AAU_ADAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0808)

#define IOP3XX_AAU_ANDAR	(volatile u32 *)IOP3XX_REG_ADDR(0x080c)

#define IOP3XX_AAU_SAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0810)

#define IOP3XX_AAU_SAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0814)

#define IOP3XX_AAU_SAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0818)

#define IOP3XX_AAU_SAR4		(volatile u32 *)IOP3XX_REG_ADDR(0x081c)

#define IOP3XX_AAU_DAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0820)

#define IOP3XX_AAU_ABCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0824)

#define IOP3XX_AAU_ADCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0828)

#define IOP3XX_AAU_SAR5		(volatile u32 *)IOP3XX_REG_ADDR(0x082c)

#define IOP3XX_AAU_SAR6		(volatile u32 *)IOP3XX_REG_ADDR(0x0830)

#define IOP3XX_AAU_SAR7		(volatile u32 *)IOP3XX_REG_ADDR(0x0834)

#define IOP3XX_AAU_SAR8		(volatile u32 *)IOP3XX_REG_ADDR(0x0838)

#define IOP3XX_AAU_EDCR0	(volatile u32 *)IOP3XX_REG_ADDR(0x083c)

#define IOP3XX_AAU_SAR9		(volatile u32 *)IOP3XX_REG_ADDR(0x0840)

#define IOP3XX_AAU_SAR10	(volatile u32 *)IOP3XX_REG_ADDR(0x0844)

#define IOP3XX_AAU_SAR11	(volatile u32 *)IOP3XX_REG_ADDR(0x0848)

#define IOP3XX_AAU_SAR12	(volatile u32 *)IOP3XX_REG_ADDR(0x084c)

#define IOP3XX_AAU_SAR13	(volatile u32 *)IOP3XX_REG_ADDR(0x0850)

#define IOP3XX_AAU_SAR14	(volatile u32 *)IOP3XX_REG_ADDR(0x0854)

#define IOP3XX_AAU_SAR15	(volatile u32 *)IOP3XX_REG_ADDR(0x0858)

#define IOP3XX_AAU_SAR16	(volatile u32 *)IOP3XX_REG_ADDR(0x085c)

#define IOP3XX_AAU_EDCR1	(volatile u32 *)IOP3XX_REG_ADDR(0x0860)

#define IOP3XX_AAU_SAR17	(volatile u32 *)IOP3XX_REG_ADDR(0x0864)

#define IOP3XX_AAU_SAR18	(volatile u32 *)IOP3XX_REG_ADDR(0x0868)

#define IOP3XX_AAU_SAR19	(volatile u32 *)IOP3XX_REG_ADDR(0x086c)

#define IOP3XX_AAU_SAR20	(volatile u32 *)IOP3XX_REG_ADDR(0x0870)

#define IOP3XX_AAU_SAR21	(volatile u32 *)IOP3XX_REG_ADDR(0x0874)

#define IOP3XX_AAU_SAR22	(volatile u32 *)IOP3XX_REG_ADDR(0x0878)

#define IOP3XX_AAU_SAR23	(volatile u32 *)IOP3XX_REG_ADDR(0x087c)

#define IOP3XX_AAU_SAR24	(volatile u32 *)IOP3XX_REG_ADDR(0x0880)

#define IOP3XX_AAU_EDCR2	(volatile u32 *)IOP3XX_REG_ADDR(0x0884)

#define IOP3XX_AAU_SAR25	(volatile u32 *)IOP3XX_REG_ADDR(0x0888)

#define IOP3XX_AAU_SAR26	(volatile u32 *)IOP3XX_REG_ADDR(0x088c)

#define IOP3XX_AAU_SAR27	(volatile u32 *)IOP3XX_REG_ADDR(0x0890)

#define IOP3XX_AAU_SAR28	(volatile u32 *)IOP3XX_REG_ADDR(0x0894)

#define IOP3XX_AAU_SAR29	(volatile u32 *)IOP3XX_REG_ADDR(0x0898)

#define IOP3XX_AAU_SAR30	(volatile u32 *)IOP3XX_REG_ADDR(0x089c)

#define IOP3XX_AAU_SAR31	(volatile u32 *)IOP3XX_REG_ADDR(0x08a0)

#define IOP3XX_AAU_SAR32	(volatile u32 *)IOP3XX_REG_ADDR(0x08a4)



/* I2C bus interface unit  */

#define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)

#define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)