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Commit 471d7ff8 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Michael Ellerman
Browse files

powerpc/64s: Remove POWER4 support 



POWER4 has been broken since at least the change 49d09bf2
("powerpc/64s: Optimise MSR handling in exception handling"), which
requires mtmsrd L=1 support. This was introduced in ISA v2.01, and
POWER4 supports ISA v2.00.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 3735eb85

arch/powerpc/Makefile

+2 −3
Original line number Diff line number Diff line
@@ -146,8 +146,8 @@ CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 $(MULTIPLEWORD) 
CFLAGS-$(CONFIG_PPC32)	+= $(call cc-option,-mno-readonly-in-sdata)



ifeq ($(CONFIG_PPC_BOOK3S_64),y)

CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,-mtune=power4)

CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=power4

CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=power7,$(call cc-option,-mtune=power5))

CFLAGS-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mcpu=power5,-mcpu=power4)

else

CFLAGS-$(CONFIG_GENERIC_CPU) += -mcpu=powerpc64

endif
@@ -168,7 +168,6 @@ ifdef CONFIG_MPROFILE_KERNEL 
endif



CFLAGS-$(CONFIG_CELL_CPU) += $(call cc-option,-mcpu=cell)

CFLAGS-$(CONFIG_POWER4_CPU) += $(call cc-option,-mcpu=power4)

CFLAGS-$(CONFIG_POWER5_CPU) += $(call cc-option,-mcpu=power5)

CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6)

CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)

arch/powerpc/include/asm/cputable.h

+2 −6
Original line number Diff line number Diff line
@@ -413,10 +413,6 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)



/* 64-bit CPUs */

#define CPU_FTRS_POWER4	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \

	    CPU_FTR_STCX_CHECKS_ADDRESS)

#define CPU_FTRS_PPC970	(CPU_FTR_LWSYNC | \

	    CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \

	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
@@ -488,7 +484,7 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_POSSIBLE	(CPU_FTRS_E6500 | CPU_FTRS_E5500)

#else

#define CPU_FTRS_POSSIBLE	\

	    (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \

	    (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \

	     CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \

	     CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \

	     CPU_FTRS_PA6T | CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | \
@@ -541,7 +537,7 @@ enum { 
#define CPU_FTRS_ALWAYS		(CPU_FTRS_E6500 & CPU_FTRS_E5500)

#else

#define CPU_FTRS_ALWAYS		\

	    (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \

	    (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \

	     CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \

	     CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \

	     CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \

arch/powerpc/include/asm/mmu.h

+3 −3
Original line number Diff line number Diff line
@@ -111,9 +111,9 @@ 
/* MMU feature bit sets for various CPUs */

#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\

	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2

#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2

#define MMU_FTRS_PPC970		MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA

#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER		MMU_FTRS_DEFAULT_HPTE_ARCH_V2

#define MMU_FTRS_PPC970		MMU_FTRS_POWER | MMU_FTR_TLBIE_CROP_VA

#define MMU_FTRS_POWER5		MMU_FTRS_POWER | MMU_FTR_LOCKLESS_TLBIE

#define MMU_FTRS_POWER6		MMU_FTRS_POWER5 | MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA

#define MMU_FTRS_POWER7		MMU_FTRS_POWER6

#define MMU_FTRS_POWER8		MMU_FTRS_POWER6

arch/powerpc/kernel/cputable.c

+3 −33
Original line number Diff line number Diff line
@@ -133,36 +133,6 @@ extern void __restore_cpu_e6500(void); 


static struct cpu_spec __initdata cpu_specs[] = {

#ifdef CONFIG_PPC_BOOK3S_64

	{	/* Power4 */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x00350000,

		.cpu_name		= "POWER4 (gp)",

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.mmu_features		= MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.pmc_type		= PPC_PMC_IBM,

		.oprofile_cpu_type	= "ppc64/power4",

		.oprofile_type		= PPC_OPROFILE_POWER4,

		.platform		= "power4",

	},

	{	/* Power4+ */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x00380000,

		.cpu_name		= "POWER4+ (gq)",

		.cpu_features		= CPU_FTRS_POWER4,

		.cpu_user_features	= COMMON_USER_POWER4,

		.mmu_features		= MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 8,

		.pmc_type		= PPC_PMC_IBM,

		.oprofile_cpu_type	= "ppc64/power4",

		.oprofile_type		= PPC_OPROFILE_POWER4,

		.platform		= "power4",

	},

	{	/* PPC970 */

		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x00390000,
@@ -628,15 +598,15 @@ static struct cpu_spec __initdata cpu_specs[] = { 
	{	/* default match */

		.pvr_mask		= 0x00000000,

		.pvr_value		= 0x00000000,

		.cpu_name		= "POWER4 (compatible)",

		.cpu_name		= "POWER5 (compatible)",

		.cpu_features		= CPU_FTRS_COMPATIBLE,

		.cpu_user_features	= COMMON_USER_PPC64,

		.mmu_features		= MMU_FTRS_DEFAULT_HPTE_ARCH_V2,

		.mmu_features		= MMU_FTRS_POWER,

		.icache_bsize		= 128,

		.dcache_bsize		= 128,

		.num_pmcs		= 6,

		.pmc_type		= PPC_PMC_IBM,

		.platform		= "power4",

		.platform		= "power5",

	}

#endif	/* CONFIG_PPC_BOOK3S_64 */

arch/powerpc/kernel/prom_init.c

+1 −9
Original line number Diff line number Diff line
@@ -1810,15 +1810,7 @@ static void __init prom_initialize_tce_table(void) 
		 * size to 4 MB.  This is enough to map 2GB of PCI DMA space.

		 * By doing this, we avoid the pitfalls of trying to DMA to

		 * MMIO space and the DMA alias hole.

		 *

		 * On POWER4, firmware sets the TCE region by assuming

		 * each TCE table is 8MB. Using this memory for anything

		 * else will impact performance, so we always allocate 8MB.

		 * Anton

		 */

		if (pvr_version_is(PVR_POWER4) || pvr_version_is(PVR_POWER4p))

			minsize = 8UL << 20;

		else

		minsize = 4UL << 20;



		/* Align to the greater of the align or size */