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Commit 46e1b3a4 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "arm64: entry: Make the trampoline cleanup optional"

parents 33710784 aa33c630

arch/arm64/include/asm/cputype.h

+6 −0
Original line number Diff line number Diff line
@@ -85,6 +85,9 @@ 
#define ARM_CPU_PART_KRYO2XX_GOLD	0x800

#define ARM_CPU_PART_KRYO2XX_SILVER	0x801

#define ARM_CPU_PART_CORTEX_A77		0xD0D

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_NEOVERSE_N1	0xD0C



#define APM_CPU_PART_POTENZA		0x000
@@ -116,6 +119,9 @@ 
#define MIDR_KRYO4G	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO4G)

#define MIDR_KRYO5S	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO5S)

#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

arch/arm64/kernel/entry.S

+10 −3
Original line number Diff line number Diff line
@@ -70,17 +70,22 @@ 


	.macro kernel_ventry, el, label, regsize = 64

	.align 7

.Lventry_start\@:

#ifdef CONFIG_UNMAP_KERNEL_AT_EL0

alternative_if ARM64_UNMAP_KERNEL_AT_EL0

	.if	\el == 0

	/*

	 * This must be the first instruction of the EL0 vector entries. It is

	 * skipped by the trampoline vectors, to trigger the cleanup.

	 */

	b	.Lskip_tramp_vectors_cleanup\@

	.if	\regsize == 64

	mrs	x30, tpidrro_el0

	msr	tpidrro_el0, xzr

	.else

	mov	x30, xzr

	.endif

.Lskip_tramp_vectors_cleanup\@:

	.endif

alternative_else_nop_endif

#endif



	sub	sp, sp, #S_FRAME_SIZE
@@ -127,6 +132,7 @@ alternative_else_nop_endif 
	mrs	x0, tpidrro_el0

#endif

	b	el\()\el\()_\label

.org .Lventry_start\@ + 128	// Did we overflow the ventry slot?

	.endm



	.macro tramp_alias, dst, sym
@@ -1014,9 +1020,10 @@ alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 
#endif

	prfm	plil1strm, [x30, #(1b - tramp_vectors)]

	msr	vbar_el1, x30

	add	x30, x30, #(1b - tramp_vectors)

	add	x30, x30, #(1b - tramp_vectors + 4)

	isb

	ret

.org 1b + 128	// Did we overflow the ventry slot?

	.endm



	.macro tramp_exit, regsize = 64