Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4695089f authored by Leonid Yegoshin's avatar Leonid Yegoshin Committed by Markos Chandras
Browse files

MIPS: Add cases for CPU_QEMU_GENERIC



Add a CPU_QEMU_GENERIC case to various switch statements.

Signed-off-by: default avatarLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent aca5721e
Loading
Loading
Loading
Loading
+7 −0
Original line number Diff line number Diff line
@@ -54,6 +54,13 @@ static inline int __pure __get_cpu_type(const int cpu_type)
	case CPU_M5150:
#endif

#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R2) || \
    defined(CONFIG_SYS_HAS_CPU_MIPS32_R6) || \
    defined(CONFIG_SYS_HAS_CPU_MIPS64_R2) || \
    defined(CONFIG_SYS_HAS_CPU_MIPS64_R6)
	case CPU_QEMU_GENERIC:
#endif

#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
	case CPU_5KC:
	case CPU_5KE:
+1 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ void __init check_wait(void)
	case CPU_PROAPTIV:
	case CPU_P5600:
	case CPU_M5150:
	case CPU_QEMU_GENERIC:
		cpu_wait = r4k_wait;
		if (read_c0_config7() & MIPS_CONF7_WII)
			cpu_wait = r4k_wait_irqoff;
+1 −0
Original line number Diff line number Diff line
@@ -208,6 +208,7 @@ void spram_config(void)
	case CPU_INTERAPTIV:
	case CPU_PROAPTIV:
	case CPU_P5600:
	case CPU_QEMU_GENERIC:
		config0 = read_c0_config();
		/* FIXME: addresses are Malta specific */
		if (config0 & (1<<24)) {
+1 −0
Original line number Diff line number Diff line
@@ -1559,6 +1559,7 @@ static inline void parity_protection_init(void)
	case CPU_INTERAPTIV:
	case CPU_PROAPTIV:
	case CPU_P5600:
	case CPU_QEMU_GENERIC:
		{
#define ERRCTL_PE	0x80000000
#define ERRCTL_L2P	0x00800000
+1 −0
Original line number Diff line number Diff line
@@ -1255,6 +1255,7 @@ static void probe_pcache(void)
	case CPU_P5600:
	case CPU_PROAPTIV:
	case CPU_M5150:
	case CPU_QEMU_GENERIC:
		if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
		    (c->icache.waysize > PAGE_SIZE))
			c->icache.flags |= MIPS_CACHE_ALIASES;
Loading