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Commit 4658aff6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-08-31' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull:

   - Mediatek has a bunch of fixes to their RDMA and Overlay engines.

   - i915 has some Cannonlake/Geminilake watermark workarounds, LSPCON
     fix, HDCP free fix, audio fix and a ppgtt reference counting fix.

   - amdgpu has some SRIOV, Kasan, memory leaks and other misc fixes"

* tag 'drm-fixes-2018-08-31' of git://anongit.freedesktop.org/drm/drm: (35 commits)
  drm/i915/audio: Hook up component bindings even if displays are disabled
  drm/i915: Increase LSPCON timeout
  drm/i915: Stop holding a ref to the ppgtt from each vma
  drm/i915: Free write_buf that we allocated with kzalloc.
  drm/i915: Fix glk/cnl display w/a #1175
  drm/amdgpu: Need to set moved to true when evict bo
  drm/amdgpu: Remove duplicated power source update
  drm/amd/display: Fix memory leak caused by missed dc_sink_release
  drm/amdgpu: fix holding mn_lock while allocating memory
  drm/amdgpu: Power on uvd block when hw_fini
  drm/amdgpu: Update power state at the end of smu hw_init.
  drm/amdgpu: Fix vce initialize failed on Kaveri/Mullins
  drm/amdgpu: Enable/disable gfx PG feature in rlc safe mode
  drm/amdgpu: Adjust the VM size based on system memory size v2
  drm/mediatek: fix connection from RDMA2 to DSI1
  drm/mediatek: update some variable name from ovl to comp
  drm/mediatek: use layer_nr function to get layer number to init plane
  drm/mediatek: add function to return RDMA layer number
  drm/mediatek: add function to return OVL layer number
  drm/mediatek: add function to get layer number for component
  ...
parents 217c3e01 49a51c4b

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+28 −19
Original line number Diff line number Diff line
@@ -1012,13 +1012,9 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 
		if (r)

			return r;



		if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {

			parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;

			if (!parser->ctx->preamble_presented) {

				parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;

				parser->ctx->preamble_presented = true;

			}

		}

		if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)

			parser->job->preamble_status |=

				AMDGPU_PREAMBLE_IB_PRESENT;



		if (parser->ring && parser->ring != ring)

			return -EINVAL;
@@ -1207,26 +1203,24 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 


	int r;



	job = p->job;

	p->job = NULL;



	r = drm_sched_job_init(&job->base, entity, p->filp);

	if (r)

		goto error_unlock;



	/* No memory allocation is allowed while holding the mn lock */

	amdgpu_mn_lock(p->mn);

	amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {

		struct amdgpu_bo *bo = e->robj;



		if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {

			amdgpu_mn_unlock(p->mn);

			return -ERESTARTSYS;

			r = -ERESTARTSYS;

			goto error_abort;

		}

	}



	job = p->job;

	p->job = NULL;



	r = drm_sched_job_init(&job->base, entity, p->filp);

	if (r) {

		amdgpu_job_free(job);

		amdgpu_mn_unlock(p->mn);

		return r;

	}



	job->owner = p->filp;

	p->fence = dma_fence_get(&job->base.s_fence->finished);
@@ -1241,6 +1235,12 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 


	amdgpu_cs_post_dependencies(p);



	if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&

	    !p->ctx->preamble_presented) {

		job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;

		p->ctx->preamble_presented = true;

	}



	cs->out.handle = seq;

	job->uf_sequence = seq;
@@ -1258,6 +1258,15 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
	amdgpu_mn_unlock(p->mn);



	return 0;



error_abort:

	dma_fence_put(&job->base.s_fence->finished);

	job->base.s_fence = NULL;



error_unlock:

	amdgpu_job_free(job);

	amdgpu_mn_unlock(p->mn);

	return r;

}



int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+2 −1
Original line number Diff line number Diff line
@@ -164,8 +164,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
		return r;

	}



	need_ctx_switch = ring->current_ctx != fence_ctx;

	if (ring->funcs->emit_pipeline_sync && job &&

	    ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) ||

	     (amdgpu_sriov_vf(adev) && need_ctx_switch) ||

	     amdgpu_vm_need_pipeline_sync(ring, job))) {

		need_pipe_sync = true;

		dma_fence_put(tmp);
@@ -196,7 +198,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	}



	skip_preamble = ring->current_ctx == fence_ctx;

	need_ctx_switch = ring->current_ctx != fence_ctx;

	if (job && ring->funcs->emit_cntxcntl) {

		if (need_ctx_switch)

			status |= AMDGPU_HAVE_CTX_SWITCH;

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+0 −8
Original line number Diff line number Diff line
@@ -1932,14 +1932,6 @@ void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) 
			amdgpu_fence_wait_empty(ring);

	}



	mutex_lock(&adev->pm.mutex);

	/* update battery/ac status */

	if (power_supply_is_system_supplied() > 0)

		adev->pm.ac_power = true;

	else

		adev->pm.ac_power = false;

	mutex_unlock(&adev->pm.mutex);



	if (adev->powerplay.pp_funcs->dispatch_tasks) {

		if (!amdgpu_device_has_dc_support(adev)) {

			mutex_lock(&adev->pm.mutex);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+30 −5
Original line number Diff line number Diff line
@@ -172,6 +172,7 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 
	 * is validated on next vm use to avoid fault.

	 * */

	list_move_tail(&base->vm_status, &vm->evicted);

	base->moved = true;

}



/**
@@ -369,7 +370,6 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, 
	uint64_t addr;

	int r;



	addr = amdgpu_bo_gpu_offset(bo);

	entries = amdgpu_bo_size(bo) / 8;



	if (pte_support_ats) {
@@ -401,6 +401,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev, 
	if (r)

		goto error;



	addr = amdgpu_bo_gpu_offset(bo);

	if (ats_entries) {

		uint64_t ats_value;
@@ -2483,28 +2484,52 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size) 
 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size

 *

 * @adev: amdgpu_device pointer

 * @vm_size: the default vm size if it's set auto

 * @min_vm_size: the minimum vm size in GB if it's set auto

 * @fragment_size_default: Default PTE fragment size

 * @max_level: max VMPT level

 * @max_bits: max address space size in bits

 *

 */

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,

			   uint32_t fragment_size_default, unsigned max_level,

			   unsigned max_bits)

{

	unsigned int max_size = 1 << (max_bits - 30);

	unsigned int vm_size;

	uint64_t tmp;



	/* adjust vm size first */

	if (amdgpu_vm_size != -1) {

		unsigned max_size = 1 << (max_bits - 30);



		vm_size = amdgpu_vm_size;

		if (vm_size > max_size) {

			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",

				 amdgpu_vm_size, max_size);

			vm_size = max_size;

		}

	} else {

		struct sysinfo si;

		unsigned int phys_ram_gb;



		/* Optimal VM size depends on the amount of physical

		 * RAM available. Underlying requirements and

		 * assumptions:

		 *

		 *  - Need to map system memory and VRAM from all GPUs

		 *     - VRAM from other GPUs not known here

		 *     - Assume VRAM <= system memory

		 *  - On GFX8 and older, VM space can be segmented for

		 *    different MTYPEs

		 *  - Need to allow room for fragmentation, guard pages etc.

		 *

		 * This adds up to a rough guess of system memory x3.

		 * Round up to power of two to maximize the available

		 * VM size with the given page table size.

		 */

		si_meminfo(&si);

		phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +

			       (1 << 30) - 1) >> 30;

		vm_size = roundup_pow_of_two(

			min(max(phys_ram_gb * 3, min_vm_size), max_size));

	}



	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+1 −1
Original line number Diff line number Diff line
@@ -321,7 +321,7 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 
void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);

void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,

		      struct amdgpu_bo_va *bo_va);

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,

void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,

			   uint32_t fragment_size_default, unsigned max_level,

			   unsigned max_bits);

int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);