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Commit 4613ca14 authored by Jerome Glisse's avatar Jerome Glisse Committed by Alex Deucher
Browse files

drm/radeon: add support for MEM_WRITE packet 



To make it easier to debug some lockup from userspace add support
to MEM_WRITE packet.

Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d3493574

drivers/gpu/drm/radeon/evergreen_cs.c

+29 −0
Original line number Diff line number Diff line
@@ -2654,6 +2654,35 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, 
			ib[idx+4] = upper_32_bits(offset) & 0xff;

		}

		break;

	case PACKET3_MEM_WRITE:

	{

		u64 offset;



		if (pkt->count != 3) {

			DRM_ERROR("bad MEM_WRITE (invalid count)\n");

			return -EINVAL;

		}

		r = evergreen_cs_packet_next_reloc(p, &reloc);

		if (r) {

			DRM_ERROR("bad MEM_WRITE (missing reloc)\n");

			return -EINVAL;

		}

		offset = radeon_get_ib_value(p, idx+0);

		offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

		if (offset & 0x7) {

			DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");

			return -EINVAL;

		}

		if ((offset + 8) > radeon_bo_size(reloc->robj)) {

			DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",

				  offset + 8, radeon_bo_size(reloc->robj));

			return -EINVAL;

		}

		offset += reloc->lobj.gpu_offset;

		ib[idx+0] = offset;

		ib[idx+1] = upper_32_bits(offset) & 0xff;

		break;

	}

	case PACKET3_COPY_DW:

		if (pkt->count != 4) {

			DRM_ERROR("bad COPY_DW (invalid count)\n");

drivers/gpu/drm/radeon/r600_cs.c

+29 −0
Original line number Diff line number Diff line
@@ -2294,6 +2294,35 @@ static int r600_packet3_check(struct radeon_cs_parser *p, 
			ib[idx+4] = upper_32_bits(offset) & 0xff;

		}

		break;

	case PACKET3_MEM_WRITE:

	{

		u64 offset;



		if (pkt->count != 3) {

			DRM_ERROR("bad MEM_WRITE (invalid count)\n");

			return -EINVAL;

		}

		r = r600_cs_packet_next_reloc(p, &reloc);

		if (r) {

			DRM_ERROR("bad MEM_WRITE (missing reloc)\n");

			return -EINVAL;

		}

		offset = radeon_get_ib_value(p, idx+0);

		offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;

		if (offset & 0x7) {

			DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");

			return -EINVAL;

		}

		if ((offset + 8) > radeon_bo_size(reloc->robj)) {

			DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",

				  offset + 8, radeon_bo_size(reloc->robj));

			return -EINVAL;

		}

		offset += reloc->lobj.gpu_offset;

		ib[idx+0] = offset;

		ib[idx+1] = upper_32_bits(offset) & 0xff;

		break;

	}

	case PACKET3_COPY_DW:

		if (pkt->count != 4) {

			DRM_ERROR("bad COPY_DW (invalid count)\n");

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -68,9 +68,10 @@ 
 *   2.25.0 - eg+: new info request for num SE and num SH

 *   2.26.0 - r600-eg: fix htile size computation

 *   2.27.0 - r600-SI: Add CS ioctl support for async DMA

 *   2.28.0 - r600-eg: Add MEM_WRITE packet support

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	27

#define KMS_DRIVER_MINOR	28

#define KMS_DRIVER_PATCHLEVEL	0

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);

int radeon_driver_unload_kms(struct drm_device *dev);