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Commit 45ce10bd authored by Mohammed Javid's avatar Mohammed Javid Committed by Gerrit - the friendly Code Review server
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data-kernel: EMAC:VT SOD BU changes 



- Added support for PHY INTR GPIO config & new name for VT
- Include HW fix is to swap mux inputs of RXC & TXC_FB.
- Included changes for VT on basis of HPG

Acked-by: default avatar <vravik&lt;vravik@qti.qualcomm.com>
          Suraj Jaiswal <jsuraj@qti.qualcomm.com>
Signed-off-by: default avatarMohammed Javid <mjavid@codeaurora.org>

Change-Id: If1464c9d13e996f84c011b32e73a80154b51fdf3
parent 367af36a

drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c

+225 −194
Original line number Diff line number Diff line
@@ -268,6 +268,8 @@ static int DWC_ETH_QOS_get_phy_intr_config(struct platform_device *pdev) 


	dwc_eth_qos_res_data.phy_intr = platform_get_irq_byname(pdev, "phy-intr");



	EMACDBG("Received IRQ number:%d\n",dwc_eth_qos_res_data.phy_intr);



	EMACDBG("Exit\n");

	return ret;

}
@@ -291,11 +293,15 @@ static void DWC_ETH_QOS_configure_gpio_pins(struct platform_device *pdev) 
	struct pinctrl_state *rgmii_rxd3_state;

	struct pinctrl_state *rgmii_rxc_state;

	struct pinctrl_state *rgmii_rx_ctl_state;

	struct pinctrl_state *emac_phy_reset_state;

	struct pinctrl_state *emac_phy_intr_state;



	int ret = 0;



	EMACDBG("Enter\n");



	if (dwc_eth_qos_res_data.is_pinctrl_names) {



		pinctrl = devm_pinctrl_get(&pdev->dev);

		if (IS_ERR_OR_NULL(pinctrl)) {

			ret = PTR_ERR(pinctrl);
@@ -311,7 +317,6 @@ static void DWC_ETH_QOS_configure_gpio_pins(struct platform_device *pdev) 
			EMACERR("Failed to get mdc_state, err = %d\n", ret);

			return;

		}



		EMACDBG("Get mdc_state succeed\n");

		ret = pinctrl_select_state(pinctrl, mdc_state);

		if (ret)
@@ -491,6 +496,33 @@ static void DWC_ETH_QOS_configure_gpio_pins(struct platform_device *pdev) 
		else

			EMACDBG("Set rgmii_rx_ctl_state succeed\n");



		emac_phy_intr_state = pinctrl_lookup_state(pinctrl, EMAC_PHY_INTR);

		if (IS_ERR_OR_NULL(emac_phy_intr_state)) {

			ret = PTR_ERR(emac_phy_intr_state);

			EMACERR("Failed to get emac_phy_intr_state, err = %d\n", ret);

			return;

		}

		EMACDBG("Get emac_phy_intr_state succeed\n");

		ret = pinctrl_select_state(pinctrl, emac_phy_intr_state);

		if (ret)

			EMACERR("Unable to set emac_phy_intr_state state, err = %d\n", ret);

		else

			EMACDBG("Set emac_phy_intr_state succeed\n");



		emac_phy_reset_state = pinctrl_lookup_state(pinctrl, EMAC_PHY_RESET);

		if (IS_ERR_OR_NULL(emac_phy_reset_state)) {

			ret = PTR_ERR(emac_phy_reset_state);

			EMACERR("Failed to get emac_phy_reset_state, err = %d\n", ret);

			return;

		}

		EMACDBG("Get emac_phy_reset_state succeed\n");

		ret = pinctrl_select_state(pinctrl, emac_phy_reset_state);

		if (ret)

			EMACERR("Unable to set emac_phy_reset_state state, err = %d\n", ret);

		else

			EMACDBG("Set emac_phy_reset_state succeed\n");

	}



	EMACDBG("Exit\n");



	return;
@@ -1065,12 +1097,11 @@ static int DWC_ETH_QOS_init_gpios(struct device *dev) 
					EMAC_GPIO_PHY_RESET_NAME);

			goto gpio_error;

		}

		EMACDBG("PHY is out of reset successfully\n");

	}



		mdelay(1);



		gpio_set_value(dwc_eth_qos_res_data.gpio_phy_reset, PHY_RESET_GPIO_HIGH);

		EMACDBG("PHY is out of reset successfully\n");

	}



	return ret;

drivers/emac-dwc-eqos/DWC_ETH_QOS_rgmii_io_macro.c

+30 −14
Original line number Diff line number Diff line
@@ -331,7 +331,17 @@ int DWC_ETH_QOS_set_rgmii_func_clk_en(void) 
 */

int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata)

{

	uint loopback_mode = 0x0;

	uint loopback_mode = 0;

	uint loopback_mode_en = 0;

	uint rgmii_data_divide_clk;

	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_0) {

		if(pdata->io_macro_phy_intf == RGMII_MODE)

			loopback_mode_en = 0x1;

		rgmii_data_divide_clk = 0x0;

	} else {

		loopback_mode_en = 0x0;

		rgmii_data_divide_clk = 0x1;

	}

	ULONG data;



	EMACDBG("Enter\n");
@@ -359,12 +369,12 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_BYPASS_TX_ID_EN_UDFWR(0x1);

				RGMII_POS_NEG_DATA_SEL_UDFWR(0x0);

				RGMII_PROG_SWAP_UDFWR(0x0);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(rgmii_data_divide_clk);

				RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x0);

				RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x0);

				/* Rx Path */

				RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);

				RGMII_LOOPBACK_EN_UDFWR(0x0);

				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0)

					RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

			} else {
@@ -376,7 +386,7 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				 * based on the programmable swap control bit

				 */

				RGMII_PROG_SWAP_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(rgmii_data_divide_clk);

				RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

				RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x0);

				/* If data arrives at positive edge or if data is
@@ -395,7 +405,7 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				SDCC_HC_REG_DDR_CONFIG_RGRD(data);

				data |= (1 << 31);

				SDCC_HC_REG_DDR_CONFIG_RGWR(data);

				RGMII_LOOPBACK_EN_UDFWR(0x0);

				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

			}

			break;
@@ -409,32 +419,35 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_BYPASS_TX_ID_EN_UDFWR(0x1);

				RGMII_POS_NEG_DATA_SEL_UDFWR(0x0);

				RGMII_PROG_SWAP_UDFWR(0x0);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(rgmii_data_divide_clk);

				RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x0);



				RGMII_MAX_SPD_PRG_2_UDFWR(0x1);

				RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x1);

				/* Rx Path */

				RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x0);

				RGMII_LOOPBACK_EN_UDFWR(0x0);

				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0)

					RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);



			} else{

				RGMII_DDR_MODE_UDFWR(0x1);

				RGMII_BYPASS_TX_ID_EN_UDFWR(0x1);

				RGMII_POS_NEG_DATA_SEL_UDFWR(0x0);

				RGMII_PROG_SWAP_UDFWR(0x0);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(rgmii_data_divide_clk);

				RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

				RGMII_MAX_SPD_PRG_2_UDFWR(0x1);

				RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x0);

				/* Rx Path */

				if (pdata->emac_hw_version_type == EMAC_HW_v2_3_0)

					RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x0);

				else

					RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);



				SDCC_HC_EXT_PRG_RCLK_DLY_CODE_UDFWR(0x5);

				SDCC_HC_EXT_PRG_RCLK_DLY_UDFWR(0x3f);

				SDCC_HC_EXT_PRG_RCLK_DLY_EN_UDFWR(0x1);

				RGMII_LOOPBACK_EN_UDFWR(0x0);

				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

			}

			break;
@@ -448,7 +461,7 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_BYPASS_TX_ID_EN_UDFWR(0x1);

				RGMII_POS_NEG_DATA_SEL_UDFWR(0x0);

				RGMII_PROG_SWAP_UDFWR(0x0);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(rgmii_data_divide_clk);

				RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x0);

				RGMII_MAX_SPD_PRG_9_UDFWR(0x13);

				RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x1);
@@ -461,17 +474,20 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_BYPASS_TX_ID_EN_UDFWR(0x1);

				RGMII_POS_NEG_DATA_SEL_UDFWR(0x0);

				RGMII_PROG_SWAP_UDFWR(0x0);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

				RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(rgmii_data_divide_clk);

				RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

				RGMII_MAX_SPD_PRG_9_UDFWR(0x13);

				RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x0);



				/* Rx Path */

                        if (pdata->emac_hw_version_type == EMAC_HW_v2_3_0)

				RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x0);

                        else

				RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);

				SDCC_HC_EXT_PRG_RCLK_DLY_CODE_UDFWR(0x5);

				SDCC_HC_EXT_PRG_RCLK_DLY_UDFWR(0x3f);

				SDCC_HC_EXT_PRG_RCLK_DLY_EN_UDFWR(0x1);

				RGMII_LOOPBACK_EN_UDFWR(0x0);

				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

			}

			break;

drivers/emac-dwc-eqos/DWC_ETH_QOS_yheader.h

+2 −0
Original line number Diff line number Diff line
@@ -1933,6 +1933,8 @@ void DWC_ETH_QOS_set_clk_and_bus_config(struct DWC_ETH_QOS_prv_data *pdata, int 
#define EMAC_RGMII_RXD3 "dev-emac-rgmii_rxd3_state"

#define EMAC_RGMII_RXC "dev-emac-rgmii_rxc_state"

#define EMAC_RGMII_RX_CTL "dev-emac-rgmii_rx_ctl_state"

#define EMAC_PHY_RESET "dev-emac-phy_reset_state"

#define EMAC_PHY_INTR "dev-emac-phy_intr"



#ifdef PER_CH_INT

void DWC_ETH_QOS_handle_DMA_Int(struct DWC_ETH_QOS_prv_data *pdata, int chinx, bool);