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Commit 45ae4df9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC fixes from Olof Johansson:

 - Fix interrupt type on ethernet switch for i.MX-based RDU2

 - GPC on i.MX exposed too large a register window which resulted in
   userspace being able to crash the machine.

 - Fixup of bad merge resolution moving GPIO DT nodes under pinctrl on
   droid4.

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: imx6: RDU2: fix irq type for mv88e6xxx switch
  soc: imx: gpc: restrict register range for regmap access
  ARM: dts: omap4-droid4: fix dts w.r.t. pwm
parents ef81e63e 5858610f
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+1 −1
Original line number Diff line number Diff line
@@ -692,7 +692,7 @@
			dsa,member = <0 0>;
			eeprom-length = <512>;
			interrupt-parent = <&gpio6>;
			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
			interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			interrupt-controller;
			#interrupt-cells = <2>;

+3 −6
Original line number Diff line number Diff line
@@ -159,13 +159,7 @@

		dais = <&mcbsp2_port>, <&mcbsp3_port>;
	};
};

&dss {
	status = "okay";
};

&gpio6 {
	pwm8: dmtimer-pwm-8 {
		pinctrl-names = "default";
		pinctrl-0 = <&vibrator_direction_pin>;
@@ -192,7 +186,10 @@
		pwm-names = "enable", "direction";
		direction-duty-cycle-ns = <10000000>;
	};
};

&dss {
	status = "okay";
};

&dsi1 {
+21 −0
Original line number Diff line number Diff line
@@ -27,9 +27,16 @@
#define GPC_PGC_SW2ISO_SHIFT	0x8
#define GPC_PGC_SW_SHIFT	0x0

#define GPC_PGC_PCI_PDN		0x200
#define GPC_PGC_PCI_SR		0x20c

#define GPC_PGC_GPU_PDN		0x260
#define GPC_PGC_GPU_PUPSCR	0x264
#define GPC_PGC_GPU_PDNSCR	0x268
#define GPC_PGC_GPU_SR		0x26c

#define GPC_PGC_DISP_PDN	0x240
#define GPC_PGC_DISP_SR		0x24c

#define GPU_VPU_PUP_REQ		BIT(1)
#define GPU_VPU_PDN_REQ		BIT(0)
@@ -318,10 +325,24 @@ static const struct of_device_id imx_gpc_dt_ids[] = {
	{ }
};

static const struct regmap_range yes_ranges[] = {
	regmap_reg_range(GPC_CNTR, GPC_CNTR),
	regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
	regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
	regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
};

static const struct regmap_access_table access_table = {
	.yes_ranges	= yes_ranges,
	.n_yes_ranges	= ARRAY_SIZE(yes_ranges),
};

static const struct regmap_config imx_gpc_regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.rd_table = &access_table,
	.wr_table = &access_table,
	.max_register = 0x2ac,
};