Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 45a5f720 authored by John Fastabend's avatar John Fastabend Committed by Jeff Kirsher
Browse files

ixgbe: DCB, X540 devices do not respond to pause frames 



DCB enabled X540 devices are not responding to pause frames
due to a missing register set that was added for these
devices that did not exist in other devices.

Signed-off-by: default avatarJohn Fastabend <john.r.fastabend@intel.com>
Tested-by: default avatarRoss Brattain <ross.b.brattain@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent e09ad236

drivers/net/ixgbe/ixgbe_dcb_82599.c

+7 −2
Original line number Diff line number Diff line
@@ -301,12 +301,17 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en) 
		IXGBE_WRITE_REG(hw, IXGBE_FCCFG, reg);

		/*

		 * Enable Receive PFC

		 * We will always honor XOFF frames we receive when

		 * we are in PFC mode.

		 * 82599 will always honor XOFF frames we receive when

		 * we are in PFC mode however X540 only honors enabled

		 * traffic classes.

		 */

		reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);

		reg &= ~IXGBE_MFLCN_RFCE;

		reg |= IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_DPF;



		if (hw->mac.type == ixgbe_mac_X540)

			reg |= pfc_en << IXGBE_MFLCN_RPFCE_SHIFT;



		IXGBE_WRITE_REG(hw, IXGBE_MFLCN, reg);



	} else {

drivers/net/ixgbe/ixgbe_type.h

+2 −0
Original line number Diff line number Diff line
@@ -1728,6 +1728,8 @@ 
#define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */

#define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */



#define IXGBE_MFLCN_RPFCE_SHIFT		 4



/* Multiple Receive Queue Control */

#define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */

#define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */