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Commit 4598874f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: configure IBI controller on Kona"

parents 84d4f71f 452cd986

bindings/i3c/qcom,geni-i3c.txt

+2 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required properties: 
- interrupts: the interrupt line connected to this I3C master.

- reg: I3C master registers.

- qcom,wrapper-core: Wrapper QUPv3 core containing this I3C controller.

- qcom,ibi-ctrl-id: IBI controller instance number.



Optional properties:

- se-clock-frequency: Source serial clock frequency to use.
@@ -45,4 +46,5 @@ Example: 
		#address-cells = <3>;

		#size-cells = <0>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,ibi-ctrl-id = <0>;

	};

qcom/kona-pinctrl.dtsi

+32 −3
Original line number Diff line number Diff line
@@ -2622,13 +2622,42 @@ 
			qupv3_se0_i3c_sleep: qupv3_se0_i3c_sleep {

				mux {

					pins = "gpio28", "gpio29";

					function = "gpio";

					function = "ibi_i3c";

				};



				config {

					pins = "gpio28", "gpio29";

					drive-strength = <2>;

					bias-disable;

					drive-strength = <16>;

					bias-pull-up;

				};

			};

		};



		/* QUPv3_0 North SE1 mappings */

		qupv3_se1_i3c_pins: qupv3_se1_i3c_pins {

			qupv3_se1_i3c_active: qupv3_se1_i3c_active {

				mux {

					pins = "gpio4", "gpio5";

					function = "ibi_i3c";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <16>;

					bias-pull-up;

				};

			};



			qupv3_se1_i3c_sleep: qupv3_se1_i3c_sleep {

				mux {

					pins = "gpio4", "gpio5";

					function = "ibi_i3c";

				};



				config {

					pins = "gpio4", "gpio5";

					drive-strength = <16>;

					bias-pull-up;

				};

			};

		};

qcom/kona-qupv3.dtsi

+28 −1
Original line number Diff line number Diff line
@@ -24,10 +24,37 @@ 
		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se0_i3c_active>;

		pinctrl-1 = <&qupv3_se0_i3c_sleep>;

		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;

		interrupts-extended = <&intc GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 31 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 30 IRQ_TYPE_LEVEL_HIGH>;



		#address-cells = <3>;

		#size-cells = <0>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,ibi-ctrl-id = <0>;

		status = "disabled";

	};



       /* QUPV3_0_SE1 */

       i3c1: i3c-master@984000 {

		compatible = "qcom,geni-i3c";

		reg = <0x984000 0x4000>,

			<0xEC40000 0x10000>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se1_i3c_active>;

		pinctrl-1 = <&qupv3_se1_i3c_sleep>;

		interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 33 IRQ_TYPE_LEVEL_HIGH>,

				<&pdc 32 IRQ_TYPE_LEVEL_HIGH>;



		#address-cells = <3>;

		#size-cells = <0>;

		qcom,wrapper-core = <&qupv3_0>;

		qcom,ibi-ctrl-id = <1>;

		status = "disabled";

	};

qcom/kona.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -2491,7 +2491,7 @@ 
	pdc: interrupt-controller@b220000 {

		compatible = "qcom,kona-pdc";

		reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;

		qcom,pdc-ranges = <0 480 30>, <42 522 52>, <94 609 30>;

		qcom,pdc-ranges = <0 480 38>, <42 522 52>, <94 609 30>;

		#interrupt-cells = <2>;

		interrupt-parent = <&intc>;

		interrupt-controller;