Merge "ARM: dts: msm: Add ddr related cti for kona"

		clock-names = "apb_pclk";

	};

	cti0_ddr0: cti@6a02000 {

	cti0_ddr0: cti@6e01000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6a02000 0x1000>;

		reg = <0x6e01000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_0_cti0";

		coresight-name = "coresight-cti-ddr_dl_0_cti_0";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti1_ddr0: cti@6a03000 {

	cti1_ddr0: cti@6e02000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6a03000 0x1000>;

		reg = <0x6e02000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_0_cti1";

		coresight-name = "coresight-cti-ddr_dl_0_cti_1";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti0_ddr1: cti@6a10000 {

	cti2_ddr0: cti@6e03000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6a10000 0x1000>;

		reg = <0x6e03000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";

		coresight-name = "coresight-cti-ddr_dl_0_cti_2";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti1_ddr1: cti@6a11000 {

	cti0_ddr1: cti@6e0c000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6a11000 0x1000>;

		reg = <0x6e0c000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";

		coresight-name = "coresight-cti-ddr_dl_1_cti_0";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti1_ddr1: cti@6e0d000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6e0d000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti_1";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti2_ddr1: cti@6e0e000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6e0e000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti_2";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti_ddr_ch02: cti@6e11000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6e11000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_ch02_dl_cti_0";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";

	};

	cti_ddr_ch13: cti@6e21000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x000bb966>;

		reg = <0x6e21000 0x1000>;

		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_ch13_dl_cti_0";

		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";