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Commit 455a70cb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - more intc updates [Yuriv]

 - fix module build when unwinder is turned off

 - IO Coherency Programming model updates

 - other miscellaneous

* tag 'arc-4.10-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: Revert "ARC: mm: IOC: Don't enable IOC by default"
  ARC: mm: split arc_cache_init to allow __init reaping of bulk
  ARCv2: IOC: Use actual memory size to setup aperture size
  ARCv2: IOC: Adhere to progamming model guidelines to avoid DMA corruption
  ARCv2: IOC: refactor the IOC and SLC operations into own functions
  ARC: module: Fix !CONFIG_ARC_DW2_UNWIND builds
  ARCv2: save r30 on kernel entry as gcc uses it for code-gen
  ARCv2: IRQ: Call entry/exit functions for chained handlers in MCIP
  ARC: IRQ: Use hwirq instead of virq in mask/unmask
  ARC: mmu: clarify the MMUv3 programming model
parents 83fd57a7 d0e73e2a

arch/arc/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ config ARC 
	select HAVE_KPROBES

	select HAVE_KRETPROBES

	select HAVE_MEMBLOCK

	select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND

	select HAVE_MOD_ARCH_SPECIFIC

	select HAVE_OPROFILE

	select HAVE_PERF_EVENTS

	select HANDLE_DOMAIN_IRQ

arch/arc/include/asm/cache.h

+5 −4
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ extern unsigned long perip_base, perip_end; 
#define ARC_REG_IC_PTAG_HI	0x1F



/* Bit val in IC_CTRL */

#define IC_CTRL_CACHE_DISABLE   0x1

#define IC_CTRL_DIS		0x1



/* Data cache related Auxiliary registers */

#define ARC_REG_DC_BCR		0x72	/* Build Config reg */
@@ -80,7 +80,8 @@ extern unsigned long perip_base, perip_end; 
#define ARC_REG_DC_PTAG_HI	0x5F



/* Bit val in DC_CTRL */

#define DC_CTRL_INV_MODE_FLUSH  0x40

#define DC_CTRL_DIS		0x001

#define DC_CTRL_INV_MODE_FLUSH	0x040

#define DC_CTRL_FLUSH_STATUS	0x100



/*System-level cache (L2 cache) related Auxiliary registers */
@@ -92,8 +93,8 @@ extern unsigned long perip_base, perip_end; 
#define ARC_REG_SLC_RGN_END	0x916



/* Bit val in SLC_CONTROL */

#define SLC_CTRL_DIS		0x001

#define SLC_CTRL_IM		0x040

#define SLC_CTRL_DISABLE	0x001

#define SLC_CTRL_BUSY		0x100

#define SLC_CTRL_RGN_OP_INV	0x200

arch/arc/include/asm/entry-arcv2.h

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
	;

	; Now manually save: r12, sp, fp, gp, r25



	PUSH	r30

	PUSH	r12



	; Saving pt_regs->sp correctly requires some extra work due to the way
@@ -72,6 +73,7 @@ 
	POPAX	AUX_USER_SP

1:

	POP	r12

	POP	r30



.endm

arch/arc/include/asm/module.h

+2 −2
Original line number Diff line number Diff line
@@ -14,13 +14,13 @@ 


#include <asm-generic/module.h>



#ifdef CONFIG_ARC_DW2_UNWIND

struct mod_arch_specific {

#ifdef CONFIG_ARC_DW2_UNWIND

	void *unw_info;

	int unw_sec_idx;

#endif

	const char *secstr;

};

#endif



#define MODULE_PROC_FAMILY "ARC700"

arch/arc/include/asm/ptrace.h

+1 −1
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ struct pt_regs { 
	unsigned long fp;

	unsigned long sp;	/* user/kernel sp depending on where we came from  */



	unsigned long r12;

	unsigned long r12, r30;



	/*------- Below list auto saved by h/w -----------*/

	unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;