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Commit 448fadc8 authored by Christoffer Dall's avatar Christoffer Dall
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arm64: mm: Add additional parameter to uaccess_ttbr0_enable



Add an extra temporary register parameter to uaccess_ttbr0_enable which
is about to be required for arm64 PAN support.

This patch doesn't introduce any functional change but ensures that the
kernel compiles once the KVM/ARM tree is merged with the arm64 tree by
ensuring a trivially mergable conflict with commit
27a921e7
("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN").

Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent 17ab9d57
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+2 −2
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ alternative_if_not ARM64_HAS_PAN
alternative_else_nop_endif
	.endm

	.macro	uaccess_ttbr0_enable, tmp1, tmp2
	.macro	uaccess_ttbr0_enable, tmp1, tmp2, tmp3
alternative_if_not ARM64_HAS_PAN
	save_and_disable_irq \tmp2		// avoid preemption
	__uaccess_ttbr0_enable \tmp1
@@ -42,7 +42,7 @@ alternative_else_nop_endif
	.macro	uaccess_ttbr0_disable, tmp1
	.endm

	.macro	uaccess_ttbr0_enable, tmp1, tmp2
	.macro	uaccess_ttbr0_enable, tmp1, tmp2, tmp3
	.endm
#endif

+2 −2
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ ENTRY(flush_icache_range)
 *	- end     - virtual end address of region
 */
ENTRY(__flush_cache_user_range)
	uaccess_ttbr0_enable x2, x3
	uaccess_ttbr0_enable x2, x3, x4
	dcache_line_size x2, x3
	sub	x3, x2, #1
	bic	x4, x0, x3
@@ -80,7 +80,7 @@ ENDPROC(__flush_cache_user_range)
 *	- end     - virtual end address of region
 */
ENTRY(invalidate_icache_range)
	uaccess_ttbr0_enable x2, x3
	uaccess_ttbr0_enable x2, x3, x4

	invalidate_icache_by_line x0, x1, x2, x3, 2f
	mov	x0, xzr
+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ ENTRY(privcmd_call)
	 * need the explicit uaccess_enable/disable if the TTBR0 PAN emulation
	 * is enabled (it implies that hardware UAO and PAN disabled).
	 */
	uaccess_ttbr0_enable x6, x7
	uaccess_ttbr0_enable x6, x7, x8
	hvc XEN_IMM

	/*