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Commit 446f2545 authored by Armin Reese's avatar Armin Reese Committed by Daniel Vetter
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drm/i915: Mask reserved bits in display/sprite address registers 



The purpose of this patch is to avoid zeroing the lower 12 reserved bits
of surface base address registers (framebuffer & sprite).  There are bits
in that range that may occasionally be set by BIOS or by other components.

Signed-off-by: default avatarArmin Reese <armin.c.reese@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 83de97c8

drivers/gpu/drm/i915/i915_irq.c

+2 −1
Original line number Diff line number Diff line
@@ -1368,7 +1368,8 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 
	obj = work->pending_flip_obj;

	if (INTEL_INFO(dev)->gen >= 4) {

		int dspsurf = DSPSURF(intel_crtc->plane);

		stall_detected = I915_READ(dspsurf) == obj->gtt_offset;

		stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==

					obj->gtt_offset;

	} else {

		int dspaddr = DSPADDR(intel_crtc->plane);

		stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +

drivers/gpu/drm/i915/i915_reg.h

+7 −0
Original line number Diff line number Diff line
@@ -2869,6 +2869,13 @@ 
#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)

#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)



/* Display/Sprite base address macros */

#define DISP_BASEADDR_MASK	(0xfffff000)

#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)

#define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)

#define I915_MODIFY_DISPBASE(reg, gfx_addr) \

		(I915_WRITE(reg, gfx_addr | I915_LO_DISPBASE(I915_READ(reg))))



/* VBIOS flags */

#define SWF00			0x71410

#define SWF01			0x71414

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -2236,7 +2236,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 
		      Start, Offset, x, y, fb->pitches[0]);

	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);

	if (INTEL_INFO(dev)->gen >= 4) {

		I915_WRITE(DSPSURF(plane), Start);

		I915_MODIFY_DISPBASE(DSPSURF(plane), Start);

		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

		I915_WRITE(DSPADDR(plane), Offset);

	} else
@@ -2316,7 +2316,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc, 
	DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",

		      Start, Offset, x, y, fb->pitches[0]);

	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);

	I915_WRITE(DSPSURF(plane), Start);

	I915_MODIFY_DISPBASE(DSPSURF(plane), Start);

	I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

	I915_WRITE(DSPADDR(plane), Offset);

	POSTING_READ(reg);

drivers/gpu/drm/i915/intel_sprite.c

+4 −4
Original line number Diff line number Diff line
@@ -133,7 +133,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);

	I915_WRITE(SPRSCALE(pipe), sprscale);

	I915_WRITE(SPRCTL(pipe), sprctl);

	I915_WRITE(SPRSURF(pipe), obj->gtt_offset);

	I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset);

	POSTING_READ(SPRSURF(pipe));

}
@@ -149,7 +149,7 @@ ivb_disable_plane(struct drm_plane *plane) 
	/* Can't leave the scaler enabled... */

	I915_WRITE(SPRSCALE(pipe), 0);

	/* Activate double buffered register update */

	I915_WRITE(SPRSURF(pipe), 0);

	I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);

	POSTING_READ(SPRSURF(pipe));

}
@@ -291,7 +291,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, 
	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);

	I915_WRITE(DVSSCALE(pipe), dvsscale);

	I915_WRITE(DVSCNTR(pipe), dvscntr);

	I915_WRITE(DVSSURF(pipe), obj->gtt_offset);

	I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset);

	POSTING_READ(DVSSURF(pipe));

}
@@ -307,7 +307,7 @@ ilk_disable_plane(struct drm_plane *plane) 
	/* Disable the scaler */

	I915_WRITE(DVSSCALE(pipe), 0);

	/* Flush double buffered register updates */

	I915_WRITE(DVSSURF(pipe), 0);

	I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);

	POSTING_READ(DVSSURF(pipe));

}