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Commit 440fc172 authored by Paul Mundt's avatar Paul Mundt
Browse files

sh: Fix up L2 cache probe. 



SH7723 is the first hard silicon to implement the L2, and unsurprisingly,
does the precise inverse of what the specification alleges. XOR the
URAM/L2 size bits to get back in line with the existing parsing logic.

Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent e5a4c65b

arch/sh/kernel/cpu/sh4/probe.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -220,6 +220,12 @@ int __init detect_cpu_and_cache_system(void) 
	 * SH-4A's have an optional PIPT L2.

	 * SH-4A's have an optional PIPT L2.

	 */

	 */

	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {

	if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {

		/* Bug if we can't decode the L2 info */

		BUG_ON(!(cvr & 0xf));



		/* Silicon and specifications have clearly never met.. */

		cvr ^= 0xf;



		/*

		/*

		 * Size calculation is much more sensible

		 * Size calculation is much more sensible

		 * than it is for the L1.

		 * than it is for the L1.