Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 43b812d9 authored by Paul Mackerras's avatar Paul Mackerras
Browse files

Merge remote-tracking branch 'remotes/powerpc/topic/ppc-kvm' into kvm-ppc-next 



This merges in the ppc-kvm topic branch of the powerpc repository
to get some changes on which future patches will depend, in particular
some new exports and TEXASR bit definitions.

Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
parents 7b0e827c eacbb218

arch/powerpc/include/asm/asm-prototypes.h

+3 −0
Original line number Diff line number Diff line
@@ -141,4 +141,7 @@ unsigned long prepare_ftrace_return(unsigned long parent, unsigned long ip); 
void pnv_power9_force_smt4_catch(void);

void pnv_power9_force_smt4_release(void);



void tm_enable(void);

void tm_disable(void);

void tm_abort(uint8_t cause);

#endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */

arch/powerpc/include/asm/reg.h

+26 −6
Original line number Diff line number Diff line
@@ -146,6 +146,12 @@ 
#define MSR_64BIT	0

#endif



/* Condition Register related */

#define CR0_SHIFT	28

#define CR0_MASK	0xF

#define CR0_TBEGIN_FAILURE	(0x2 << 28) /* 0b0010 */





/* Power Management - Processor Stop Status and Control Register Fields */

#define PSSCR_RL_MASK		0x0000000F /* Requested Level */

#define PSSCR_MTL_MASK		0x000000F0 /* Maximum Transition Level */
@@ -239,13 +245,27 @@ 
#define SPRN_TFIAR	0x81	/* Transaction Failure Inst Addr   */

#define SPRN_TEXASR	0x82	/* Transaction EXception & Summary */

#define SPRN_TEXASRU	0x83	/* ''	   ''	   ''	 Upper 32  */

#define   TEXASR_ABORT	__MASK(63-31) /* terminated by tabort or treclaim */

#define   TEXASR_SUSP	__MASK(63-32) /* tx failed in suspended state */

#define   TEXASR_HV	__MASK(63-34) /* MSR[HV] when failure occurred */

#define   TEXASR_PR	__MASK(63-35) /* MSR[PR] when failure occurred */

#define   TEXASR_FS	__MASK(63-36) /* TEXASR Failure Summary */

#define   TEXASR_EXACT	__MASK(63-37) /* TFIAR value is exact */



#define TEXASR_FC_LG	(63 - 7)	/* Failure Code */

#define TEXASR_AB_LG	(63 - 31)	/* Abort */

#define TEXASR_SU_LG	(63 - 32)	/* Suspend */

#define TEXASR_HV_LG	(63 - 34)	/* Hypervisor state*/

#define TEXASR_PR_LG	(63 - 35)	/* Privilege level */

#define TEXASR_FS_LG	(63 - 36)	/* failure summary */

#define TEXASR_EX_LG	(63 - 37)	/* TFIAR exact bit */

#define TEXASR_ROT_LG	(63 - 38)	/* ROT bit */



#define   TEXASR_ABORT	__MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */

#define   TEXASR_SUSP	__MASK(TEXASR_SU_LG) /* tx failed in suspended state */

#define   TEXASR_HV	__MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */

#define   TEXASR_PR	__MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */

#define   TEXASR_FS	__MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */

#define   TEXASR_EXACT	__MASK(TEXASR_EX_LG) /* TFIAR value is exact */

#define   TEXASR_ROT	__MASK(TEXASR_ROT_LG)

#define   TEXASR_FC	(ASM_CONST(0xFF) << TEXASR_FC_LG)



#define SPRN_TFHAR	0x80	/* Transaction Failure Handler Addr */



#define SPRN_TIDR	144	/* Thread ID register */

#define SPRN_CTRLF	0x088

#define SPRN_CTRLT	0x098

arch/powerpc/include/asm/tm.h

+0 −2
Original line number Diff line number Diff line
@@ -10,12 +10,10 @@ 


#ifndef __ASSEMBLY__



extern void tm_enable(void);

extern void tm_reclaim(struct thread_struct *thread,

		       uint8_t cause);

extern void tm_reclaim_current(uint8_t cause);

extern void tm_recheckpoint(struct thread_struct *thread);

extern void tm_abort(uint8_t cause);

extern void tm_save_sprs(struct thread_struct *thread);

extern void tm_restore_sprs(struct thread_struct *thread);

arch/powerpc/kernel/process.c

+1 −0
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ unsigned long msr_check_and_set(unsigned long bits) 


	return newmsr;

}

EXPORT_SYMBOL_GPL(msr_check_and_set);



void __msr_check_and_clear(unsigned long bits)

{

arch/powerpc/kernel/tm.S

+12 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <asm/ptrace.h>

#include <asm/reg.h>

#include <asm/bug.h>

#include <asm/export.h>



#ifdef CONFIG_VSX

/* See fpu.S, this is borrowed from there */
@@ -55,6 +56,16 @@ _GLOBAL(tm_enable) 
	or	r4, r4, r3

	mtmsrd	r4

1:	blr

EXPORT_SYMBOL_GPL(tm_enable);



_GLOBAL(tm_disable)

	mfmsr	r4

	li	r3, MSR_TM >> 32

	sldi	r3, r3, 32

	andc	r4, r4, r3

	mtmsrd	r4

	blr

EXPORT_SYMBOL_GPL(tm_disable);



_GLOBAL(tm_save_sprs)

	mfspr	r0, SPRN_TFHAR
@@ -78,6 +89,7 @@ _GLOBAL(tm_restore_sprs) 
_GLOBAL(tm_abort)

	TABORT(R3)

	blr

EXPORT_SYMBOL_GPL(tm_abort);



/* void tm_reclaim(struct thread_struct *thread,

 *		   uint8_t cause)