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Commit 42e0372c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull more ARC updates from Vineet Gupta:

 - Fix for aliasing VIPT dcache in old ARC700 cores

 - micro-optimization in ARC700 ProtV handler

 - Enable SG_CHAIN  [Vladimir]

 - ARC HS38 core intc default to prio 1

* tag 'arc-4.10-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: mm: arc700: Don't assume 2 colours for aliasing VIPT dcache
  ARC: mm: No need to save cache version in @cpuinfo
  ARC: enable SG chaining
  ARCv2: intc: default all interrupts to priority 1
  ARCv2: entry: document intr disable in hard isr
  ARC: ARCompact entry: elide re-reading ECR in ProtV handler
parents 50f6584e 08fe0079

Documentation/features/io/sg-chain/arch-support.txt

+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 
    |         arch |status|

    -----------------------

    |       alpha: | TODO |

    |         arc: | TODO |

    |         arc: |  ok  |

    |         arm: |  ok  |

    |       arm64: |  ok  |

    |       avr32: | TODO |

arch/arc/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
config ARC

	def_bool y

	select ARC_TIMERS

	select ARCH_HAS_SG_CHAIN

	select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC

	select BUILDTIME_EXTABLE_SORT

	select CLONE_BACKWARDS

arch/arc/include/asm/arcregs.h

+1 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ struct cpuinfo_arc_mmu { 
};



struct cpuinfo_arc_cache {

	unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;

	unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;

};



struct cpuinfo_arc_bpu {

arch/arc/include/asm/cacheflush.h

+4 −2
Original line number Diff line number Diff line
@@ -85,6 +85,10 @@ void flush_anon_page(struct vm_area_struct *vma, 
 */

#define PG_dc_clean	PG_arch_1



#define CACHE_COLORS_NUM	4

#define CACHE_COLORS_MSK	(CACHE_COLORS_NUM - 1)

#define CACHE_COLOR(addr)	(((unsigned long)(addr) >> (PAGE_SHIFT)) & CACHE_COLORS_MSK)



/*

 * Simple wrapper over config option

 * Bootup code ensures that hardware matches kernel configuration
@@ -94,8 +98,6 @@ static inline int cache_is_vipt_aliasing(void) 
	return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);

}



#define CACHE_COLOR(addr)	(((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)



/*

 * checks if two addresses (after page aligning) index into same cache set

 */

arch/arc/include/asm/irqflags-arcv2.h

+3 −3
Original line number Diff line number Diff line
@@ -38,10 +38,10 @@ 
#define AUX_IRQ_ACT_BIT_U	31



/*

 * User space should be interruptable even by lowest prio interrupt

 * Safe even if actual interrupt priorities is fewer or even one

 * Hardware supports 16 priorities (0 highest, 15 lowest)

 * Linux by default runs at 1, priority 0 reserved for NMI style interrupts

 */

#define ARCV2_IRQ_DEF_PRIO	15

#define ARCV2_IRQ_DEF_PRIO	1



/* seed value for status register */

#define ISA_INIT_STATUS_BITS	(STATUS_IE_MASK | STATUS_AD_MASK | \