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Commit 42a389e9 authored by Alok Chauhan's avatar Alok Chauhan Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add QUPV3 SE device node for I3C on kona



Add initial device tree node for QUPV3 i3C instance.

Change-Id: Ifb620080d85adb779f344e9959fa956b3e114212
Signed-off-by: default avatarAlok Chauhan <alokc@codeaurora.org>
parent 81f04f4f
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+29 −1
Original line number Diff line number Diff line
@@ -2538,7 +2538,35 @@
			};
		};

		/* QUPv3_0 North SE mappings */
		/* QUPv3_0 North SE0 mappings */
		qupv3_se0_i3c_pins: qupv3_se0_i3c_pins {
			qupv3_se0_i3c_active: qupv3_se0_i3c_active {
				mux {
					pins = "gpio28", "gpio29";
					function = "ibi_i3c";
				};

				config {
					pins = "gpio28", "gpio29";
					drive-strength = <16>;
					bias-pull-up;
				};
			};

			qupv3_se0_i3c_sleep: qupv3_se0_i3c_sleep {
				mux {
					pins = "gpio28", "gpio29";
					function = "gpio";
				};

				config {
					pins = "gpio28", "gpio29";
					drive-strength = <2>;
					bias-disable;
				};
			};
		};

		/* SE 0 pin mappings */
		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
			qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+18 −0
Original line number Diff line number Diff line
@@ -17,6 +17,24 @@
		qcom,iommu-dma = "bypass";
	};

	/* QUPV3_0_SE0 */
	i3c0: i3c@980000 {
		compatible = "qcom,geni-i3c";
		reg = <0x980000 0x4000>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i3c_active>;
		pinctrl-1 = <&qupv3_se0_i3c_sleep>;
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <3>;
		#size-cells = <0>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
	};

	/* Debug UART Instance for RUMI platform */
	qupv3_se2_2uart: qcom,qup_uart@988000 {
		compatible = "qcom,msm-geni-console";