Merge "clk: qcom: rpmcc: Add support for HWKM & PKA clock for Scuba" (423b46b3) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/clk-smd-rpm.c

+7 −1

Original line number	Original line	Diff line number	Diff line
	@@ -861,6 +861,8 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(scuba, ln_bb_clk2, ln_bb_clk2_a, 0x2);
	DEFINE_CLK_SMD_RPM_XO_BUFFER(scuba, rf_clk3, rf_clk3_a, 6);		DEFINE_CLK_SMD_RPM_XO_BUFFER(scuba, rf_clk3, rf_clk3_a, 6);

	DEFINE_CLK_SMD_RPM(scuba, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);		DEFINE_CLK_SMD_RPM(scuba, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
			DEFINE_CLK_SMD_RPM(scuba, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
			DEFINE_CLK_SMD_RPM(scuba, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);

	/* Scuba */		/* Scuba */
	static struct clk_hw *scuba_clks[] = {		static struct clk_hw *scuba_clks[] = {
	@@ -946,11 +948,15 @@ static struct clk_hw *scuba_clks[] = {
	[CXO_SMD_WLAN_CLK] = &bi_tcxo_wlan_clk.hw,		[CXO_SMD_WLAN_CLK] = &bi_tcxo_wlan_clk.hw,
	[CXO_SMD_PIL_LPASS_CLK] = &bi_tcxo_pil_lpass_clk.hw,		[CXO_SMD_PIL_LPASS_CLK] = &bi_tcxo_pil_lpass_clk.hw,
	[CXO_SMD_PIL_CDSP_CLK] = &bi_tcxo_pil_cdsp_clk.hw,		[CXO_SMD_PIL_CDSP_CLK] = &bi_tcxo_pil_cdsp_clk.hw,
			[RPM_SMD_HWKM_CLK] = &scuba_hwkm_clk.hw,
			[RPM_SMD_HWKM_A_CLK] = &scuba_hwkm_a_clk.hw,
			[RPM_SMD_PKA_CLK] = &scuba_pka_clk.hw,
			[RPM_SMD_PKA_A_CLK] = &scuba_pka_a_clk.hw,
	};		};

	static const struct rpm_smd_clk_desc rpm_clk_scuba = {		static const struct rpm_smd_clk_desc rpm_clk_scuba = {
	.clks = scuba_clks,		.clks = scuba_clks,
	.num_rpm_clks = RPM_SMD_CE1_A_CLK,		.num_rpm_clks = RPM_SMD_PKA_A_CLK,
	.num_clks = ARRAY_SIZE(scuba_clks),		.num_clks = ARRAY_SIZE(scuba_clks),
	};		};

include/dt-bindings/clock/qcom,rpmcc.h

+87 −83

Original line number	Original line	Diff line number	Diff line
	@@ -127,88 +127,92 @@
	#define RPM_SMD_QPIC_A_CLK 75		#define RPM_SMD_QPIC_A_CLK 75
	#define RPM_SMD_CE1_CLK 76		#define RPM_SMD_CE1_CLK 76
	#define RPM_SMD_CE1_A_CLK 77		#define RPM_SMD_CE1_A_CLK 77
	#define RPM_SMD_BIMC_GPU_CLK 78		#define RPM_SMD_HWKM_CLK 78
	#define RPM_SMD_BIMC_GPU_A_CLK 79		#define RPM_SMD_HWKM_A_CLK 79
	#define RPM_SMD_LN_BB_CLK 80		#define RPM_SMD_PKA_CLK 80
	#define RPM_SMD_LN_BB_CLK_A 81		#define RPM_SMD_PKA_A_CLK 81
	#define RPM_SMD_LN_BB_CLK_PIN 82		#define RPM_SMD_BIMC_GPU_CLK 82
	#define RPM_SMD_LN_BB_CLK_A_PIN 83		#define RPM_SMD_BIMC_GPU_A_CLK 83
	#define RPM_SMD_RF_CLK3 84		#define RPM_SMD_LN_BB_CLK 84
	#define RPM_SMD_RF_CLK3_A 85		#define RPM_SMD_LN_BB_CLK_A 85
	#define RPM_SMD_RF_CLK3_PIN 86		#define RPM_SMD_LN_BB_CLK_PIN 86
	#define RPM_SMD_RF_CLK3_A_PIN 87		#define RPM_SMD_LN_BB_CLK_A_PIN 87
	#define RPM_SMD_LN_BB_CLK1 88		#define RPM_SMD_RF_CLK3 88
	#define RPM_SMD_LN_BB_CLK1_A 89		#define RPM_SMD_RF_CLK3_A 89
	#define RPM_SMD_LN_BB_CLK2 90		#define RPM_SMD_RF_CLK3_PIN 90
	#define RPM_SMD_LN_BB_CLK2_A 91		#define RPM_SMD_RF_CLK3_A_PIN 91
	#define RPM_SMD_LN_BB_CLK3 92		#define RPM_SMD_LN_BB_CLK1 92
	#define RPM_SMD_LN_BB_CLK3_A 93		#define RPM_SMD_LN_BB_CLK1_A 93
	#define RPM_SMD_MMAXI_CLK 94		#define RPM_SMD_LN_BB_CLK2 94
	#define RPM_SMD_MMAXI_A_CLK 95		#define RPM_SMD_LN_BB_CLK2_A 95
	#define RPM_SMD_AGGR1_NOC_CLK 96		#define RPM_SMD_LN_BB_CLK3 96
	#define RPM_SMD_AGGR1_NOC_A_CLK 97		#define RPM_SMD_LN_BB_CLK3_A 97
	#define RPM_SMD_AGGR2_NOC_CLK 98		#define RPM_SMD_MMAXI_CLK 98
	#define RPM_SMD_AGGR2_NOC_A_CLK 99		#define RPM_SMD_MMAXI_A_CLK 99
	#define PNOC_MSMBUS_CLK 100		#define RPM_SMD_AGGR1_NOC_CLK 100
	#define PNOC_MSMBUS_A_CLK 101		#define RPM_SMD_AGGR1_NOC_A_CLK 101
	#define PNOC_KEEPALIVE_A_CLK 102		#define RPM_SMD_AGGR2_NOC_CLK 102
	#define SNOC_MSMBUS_CLK 103		#define RPM_SMD_AGGR2_NOC_A_CLK 103
	#define SNOC_MSMBUS_A_CLK 104		#define PNOC_MSMBUS_CLK 104
	#define BIMC_MSMBUS_CLK 105		#define PNOC_MSMBUS_A_CLK 105
	#define BIMC_MSMBUS_A_CLK 106		#define PNOC_KEEPALIVE_A_CLK 106
	#define PNOC_USB_CLK 107		#define SNOC_MSMBUS_CLK 107
	#define PNOC_USB_A_CLK 108		#define SNOC_MSMBUS_A_CLK 108
	#define SNOC_USB_CLK 109		#define BIMC_MSMBUS_CLK 109
	#define SNOC_USB_A_CLK 110		#define BIMC_MSMBUS_A_CLK 110
	#define BIMC_USB_CLK 111		#define PNOC_USB_CLK 111
	#define BIMC_USB_A_CLK 112		#define PNOC_USB_A_CLK 112
	#define SNOC_WCNSS_A_CLK 113		#define SNOC_USB_CLK 113
	#define BIMC_WCNSS_A_CLK 114		#define SNOC_USB_A_CLK 114
	#define MCD_CE1_CLK 115		#define BIMC_USB_CLK 115
	#define QCEDEV_CE1_CLK 116		#define BIMC_USB_A_CLK 116
	#define QCRYPTO_CE1_CLK 117		#define SNOC_WCNSS_A_CLK 117
	#define QSEECOM_CE1_CLK 118		#define BIMC_WCNSS_A_CLK 118
	#define SCM_CE1_CLK 119		#define MCD_CE1_CLK 119
	#define CXO_SMD_OTG_CLK 120		#define QCEDEV_CE1_CLK 120
	#define CXO_SMD_LPM_CLK 121		#define QCRYPTO_CE1_CLK 121
	#define CXO_SMD_PIL_PRONTO_CLK 122		#define QSEECOM_CE1_CLK 122
	#define CXO_SMD_PIL_MSS_CLK 123		#define SCM_CE1_CLK 123
	#define CXO_SMD_WLAN_CLK 124		#define CXO_SMD_OTG_CLK 124
	#define CXO_SMD_PIL_LPASS_CLK 125		#define CXO_SMD_LPM_CLK 125
	#define CXO_SMD_PIL_CDSP_CLK 126		#define CXO_SMD_PIL_PRONTO_CLK 126
	#define CNOC_MSMBUS_CLK 127		#define CXO_SMD_PIL_MSS_CLK 127
	#define CNOC_MSMBUS_A_CLK 128		#define CXO_SMD_WLAN_CLK 128
	#define CNOC_KEEPALIVE_A_CLK 129		#define CXO_SMD_PIL_LPASS_CLK 129
	#define SNOC_KEEPALIVE_A_CLK 130		#define CXO_SMD_PIL_CDSP_CLK 130
	#define CPP_MMNRT_MSMBUS_CLK 131		#define CNOC_MSMBUS_CLK 131
	#define CPP_MMNRT_MSMBUS_A_CLK 132		#define CNOC_MSMBUS_A_CLK 132
	#define JPEG_MMNRT_MSMBUS_CLK 133		#define CNOC_KEEPALIVE_A_CLK 133
	#define JPEG_MMNRT_MSMBUS_A_CLK 134		#define SNOC_KEEPALIVE_A_CLK 134
	#define VENUS_MMNRT_MSMBUS_CLK 135		#define CPP_MMNRT_MSMBUS_CLK 135
	#define VENUS_MMNRT_MSMBUS_A_CLK 136		#define CPP_MMNRT_MSMBUS_A_CLK 136
	#define ARM9_MMNRT_MSMBUS_CLK 137		#define JPEG_MMNRT_MSMBUS_CLK 137
	#define ARM9_MMNRT_MSMBUS_A_CLK 138		#define JPEG_MMNRT_MSMBUS_A_CLK 138
	#define MDP_MMRT_MSMBUS_CLK 139		#define VENUS_MMNRT_MSMBUS_CLK 139
	#define MDP_MMRT_MSMBUS_A_CLK 140		#define VENUS_MMNRT_MSMBUS_A_CLK 140
	#define VFE_MMRT_MSMBUS_CLK 141		#define ARM9_MMNRT_MSMBUS_CLK 141
	#define VFE_MMRT_MSMBUS_A_CLK 142		#define ARM9_MMNRT_MSMBUS_A_CLK 142
	#define QUP0_MSMBUS_SNOC_PERIPH_CLK 143		#define MDP_MMRT_MSMBUS_CLK 143
	#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK 144		#define MDP_MMRT_MSMBUS_A_CLK 144
	#define QUP1_MSMBUS_SNOC_PERIPH_CLK 145		#define VFE_MMRT_MSMBUS_CLK 145
	#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK 146		#define VFE_MMRT_MSMBUS_A_CLK 146
	#define QUP2_MSMBUS_SNOC_PERIPH_CLK 147		#define QUP0_MSMBUS_SNOC_PERIPH_CLK 147
	#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK 148		#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK 148
	#define DAP_MSMBUS_SNOC_PERIPH_CLK 149		#define QUP1_MSMBUS_SNOC_PERIPH_CLK 149
	#define DAP_MSMBUS_SNOC_PERIPH_A_CLK 150		#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK 150
	#define SDC1_MSMBUS_SNOC_PERIPH_CLK 151		#define QUP2_MSMBUS_SNOC_PERIPH_CLK 151
	#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK 152		#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK 152
	#define SDC2_MSMBUS_SNOC_PERIPH_CLK 153		#define DAP_MSMBUS_SNOC_PERIPH_CLK 153
	#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK 154		#define DAP_MSMBUS_SNOC_PERIPH_A_CLK 154
	#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK 155		#define SDC1_MSMBUS_SNOC_PERIPH_CLK 155
	#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK 156		#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK 156
	#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK 157		#define SDC2_MSMBUS_SNOC_PERIPH_CLK 157
	#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK 158		#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK 158
	#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK 159		#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK 159
	#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK 160		#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK 160
			#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK 161
			#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK 162
			#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK 163
			#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK 164

	#endif		#endif

include/linux/soc/qcom/smd-rpm.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -34,6 +34,8 @@ struct qcom_smd_rpm;
	#define QCOM_SMD_RPM_AGGR_CLK 0x72676761		#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
	#define QCOM_SMD_RPM_QUP_CLK 0x00707571		#define QCOM_SMD_RPM_QUP_CLK 0x00707571
	#define QCOM_SMD_RPM_MMXI_CLK 0x69786D6D		#define QCOM_SMD_RPM_MMXI_CLK 0x69786D6D
			#define QCOM_SMD_RPM_HWKM_CLK 0x6D6B7768
			#define QCOM_SMD_RPM_PKA_CLK 0x616B70

	int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,		int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
	int state,		int state,