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Commit 41bab9d3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: ipa: Enable deaggregation for MHIP DL pipe"

parents 6e5454c6 e3427496

drivers/platform/msm/ipa/ipa_v3/ipa_mpm.c

+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ static struct ipa_ep_cfg mhip_dl_teth_ep_cfg = { 
		.hdr_payload_len_inc_padding = true,

	},

	.aggr = {

		.aggr_en = IPA_BYPASS_AGGR, /* temporarily disabled */

		.aggr_en = IPA_ENABLE_DEAGGR,

		.aggr = IPA_QCMAP,

		.aggr_byte_limit = TETH_AGGR_DL_BYTE_LIMIT,

		.aggr_time_limit = TETH_AGGR_TIME_LIMIT,

drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c

+0 −1
Original line number Diff line number Diff line
@@ -1952,7 +1952,6 @@ int ipa3_qmi_set_aggr_info(enum ipa_aggr_enum_type_v01 aggr_enum_type) 
	/* replace to right qmap format */

	aggr_req.aggr_info[1].aggr_type = aggr_enum_type;

	aggr_req.aggr_info[2].aggr_type = aggr_enum_type;

	aggr_req.aggr_info[2].pkt_count = 1; /*disable aggregation */

	aggr_req.aggr_info[3].aggr_type = aggr_enum_type;

	aggr_req.aggr_info[4].aggr_type = aggr_enum_type;

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+5 −5
Original line number Diff line number Diff line
@@ -1936,32 +1936,32 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 


	/* MHI PRIME PIPES - Client producer / IPA Consumer pipes */

	[IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_DPL_PROD] = {

			true, IPA_v4_0_MHI_GROUP_PCIE,

			true, IPA_v4_0_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{7, 9, 8, 16, IPA_EE_AP } },

	[IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_TETH_PROD] = {

			true, IPA_v4_0_MHI_GROUP_PCIE,

			true, IPA_v4_0_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			{ 1, 0, 8, 16, IPA_EE_AP } },

	[IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_RMNET_PROD] = {

			true, IPA_v4_0_MHI_GROUP_PCIE,

			true, IPA_v4_0_GROUP_UL_DL,

			true,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			{ 2, 3, 16, 32, IPA_EE_AP } },

	/* MHI PRIME PIPES - Client Consumer / IPA Producer pipes */

	[IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_TETH_CONS] = {

			true, IPA_v4_0_MHI_GROUP_PCIE,

			true, IPA_v4_0_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			{ 20, 13, 9, 9, IPA_EE_AP } },

	[IPA_4_1_APQ][IPA_CLIENT_MHI_PRIME_RMNET_CONS] = {

			true, IPA_v4_0_MHI_GROUP_PCIE,

			true, IPA_v4_0_GROUP_UL_DL,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,