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Commit 41ba653f authored by Jie Zhang's avatar Jie Zhang Committed by Mike Frysinger
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Blackfin: decouple unrelated cache settings to get exact behavior 



The current cache options don't really represent the hardware features.
They end up setting different aspects of the hardware so that the end
result is to turn on/off the cache.  Unfortunately, when we hit cache
problems with the hardware, it's difficult to test different settings to
root cause the problem.  The current settings also don't cleanly allow for
different caching behaviors with different regions of memory.

So split the configure options such that they properly reflect the settings
that are applied to the hardware.

Signed-off-by: default avatarJie Zhang <jie.zhang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 7c039a90

arch/blackfin/Kconfig

+39 −18
Original line number Diff line number Diff line
@@ -907,23 +907,41 @@ endchoice 




comment "Cache Support"



config BFIN_ICACHE

	bool "Enable ICACHE"

	default y

config BFIN_ICACHE_LOCK

	bool "Enable Instruction Cache Locking"

	depends on BFIN_ICACHE

	default n

config BFIN_EXTMEM_ICACHEABLE

	bool "Enable ICACHE for external memory"

	depends on BFIN_ICACHE

	default y

config BFIN_L2_ICACHEABLE

	bool "Enable ICACHE for L2 SRAM"

	depends on BFIN_ICACHE

	depends on BF54x || BF561

	default n



config BFIN_DCACHE

	bool "Enable DCACHE"

	default y

config BFIN_DCACHE_BANKA

	bool "Enable only 16k BankA DCACHE - BankB is SRAM"

	depends on BFIN_DCACHE && !BF531

	default n

config BFIN_ICACHE_LOCK

	bool "Enable Instruction Cache Locking"



choice

	prompt "External memory cache policy"

config BFIN_EXTMEM_DCACHEABLE

	bool "Enable DCACHE for external memory"

	depends on BFIN_DCACHE

	default BFIN_WB if !SMP

	default BFIN_WT if SMP

config BFIN_WB

	default y

choice

	prompt "External memory DCACHE policy"

	depends on BFIN_EXTMEM_DCACHEABLE

	default BFIN_EXTMEM_WRITEBACK if !SMP

	default BFIN_EXTMEM_WRITETHROUGH if SMP

config BFIN_EXTMEM_WRITEBACK

	bool "Write back"

	depends on !SMP

	help
@@ -941,7 +959,7 @@ config BFIN_WB 
	  If you are unsure of the options and you want to be safe,

	  then go with Write Through.



config BFIN_WT

config BFIN_EXTMEM_WRITETHROUGH

	bool "Write through"

	help

	  Write Back Policy:
@@ -960,23 +978,26 @@ config BFIN_WT 


endchoice



config BFIN_L2_DCACHEABLE

	bool "Enable DCACHE for L2 SRAM"

	depends on BFIN_DCACHE

	depends on BF54x || BF561

	default n

choice

	prompt "L2 SRAM cache policy"

	depends on (BF54x || BF561)

	default BFIN_L2_WT

config BFIN_L2_WB

	prompt "L2 SRAM DCACHE policy"

	depends on BFIN_L2_DCACHEABLE

	default BFIN_L2_WRITEBACK

config BFIN_L2_WRITEBACK

	bool "Write back"

	depends on !SMP



config BFIN_L2_WT

config BFIN_L2_WRITETHROUGH

	bool "Write through"

	depends on !SMP



config BFIN_L2_NOT_CACHED

	bool "Not cached"



endchoice





comment "Memory Protection Unit"

config MPU

	bool "Enable the memory protection unit (EXPERIMENTAL)"

	default n

arch/blackfin/include/asm/cache.h

+2 −2
Original line number Diff line number Diff line
@@ -35,10 +35,10 @@ 


#if defined(CONFIG_SMP) && \

    !defined(CONFIG_BFIN_CACHE_COHERENT)

# if defined(CONFIG_BFIN_ICACHE)

# if defined(CONFIG_BFIN_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)

# define __ARCH_SYNC_CORE_ICACHE

# endif

# if defined(CONFIG_BFIN_DCACHE)

# if defined(CONFIG_BFIN_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)

# define __ARCH_SYNC_CORE_DCACHE

# endif

#ifndef __ASSEMBLY__

arch/blackfin/include/asm/cacheflush.h

+5 −5
Original line number Diff line number Diff line
@@ -56,7 +56,7 @@ extern void blackfin_invalidate_entire_icache(void); 


static inline void flush_icache_range(unsigned start, unsigned end)

{

#if defined(CONFIG_BFIN_WB)

#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)

	blackfin_dcache_flush_range(start, end);

#endif
@@ -87,7 +87,7 @@ do { memcpy(dst, src, len); \ 
#else

# define invalidate_dcache_range(start,end)	do { } while (0)

#endif

#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)

#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)

# define flush_dcache_range(start,end)		blackfin_dcache_flush_range((start), (end))

# define flush_dcache_page(page)		blackfin_dflush_page(page_address(page))

#else
@@ -100,7 +100,7 @@ extern unsigned long reserved_mem_icache_on; 


static inline int bfin_addr_dcacheable(unsigned long addr)

{

#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE

	if (addr < (_ramend - DMA_UNCACHED_REGION))

		return 1;

#endif
@@ -109,7 +109,7 @@ static inline int bfin_addr_dcacheable(unsigned long addr) 
		addr >= _ramend && addr < physical_mem_end)

		return 1;



#ifndef CONFIG_BFIN_L2_NOT_CACHED

#ifdef CONFIG_BFIN_L2_DCACHEABLE

	if (addr >= L2_START && addr < L2_START + L2_LENGTH)

		return 1;

#endif

arch/blackfin/include/asm/cplb.h

+17 −15
Original line number Diff line number Diff line
@@ -37,8 +37,6 @@ 
#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)

#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)



/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/



#if ANOMALY_05000158

#define ANOMALY_05000158_WORKAROUND             0x200

#else
@@ -47,10 +45,12 @@ 


#define CPLB_COMMON	(CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)



#ifdef CONFIG_BFIN_WB         /*Write Back Policy */

#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK

#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)

#else                           /*Write Through */

#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)

#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)

#else

#define SDRAM_DGENERIC   (CPLB_COMMON)

#endif



#define SDRAM_DNON_CHBL  (CPLB_COMMON)
@@ -61,21 +61,23 @@ 


#ifdef CONFIG_SMP

#define L2_ATTR          (INITIAL_T | I_CPLB | D_CPLB)

#define L2_IMEMORY       (CPLB_COMMON)

#define L2_DMEMORY       (CPLB_LOCK | CPLB_COMMON)

#define L2_IMEMORY       (CPLB_COMMON | PAGE_SIZE_1MB)

#define L2_DMEMORY       (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)



#else

#define L2_ATTR          (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)

#define L2_IMEMORY       (SDRAM_IGENERIC)



# if defined(CONFIG_BFIN_L2_WB)

# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_COMMON)

# elif defined(CONFIG_BFIN_L2_WT)

# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)

# elif defined(CONFIG_BFIN_L2_NOT_CACHED)

# define L2_DMEMORY      (CPLB_COMMON)

# if defined(CONFIG_BFIN_L2_ICACHEABLE)

# define L2_IMEMORY      (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)

# else

# define L2_IMEMORY      (               CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)

# endif



# if defined(CONFIG_BFIN_L2_WRITEBACK)

# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)

# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)

# define L2_DMEMORY      (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)

# else

# define L2_DMEMORY      (0)

# define L2_DMEMORY      (CPLB_COMMON | PAGE_SIZE_1MB)

# endif

#endif /* CONFIG_SMP */

arch/blackfin/kernel/cplb-mpu/cplbinit.c

+5 −5
Original line number Diff line number Diff line
@@ -46,13 +46,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) 


	printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");



#ifdef CONFIG_BFIN_ICACHE

#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE

	i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;

#endif



#ifdef CONFIG_BFIN_DCACHE

#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE

	d_cache = CPLB_L1_CHBL;

#ifdef CONFIG_BFIN_WT

#ifdef CONFIG_BFIN_EXTMEM_WRITETROUGH

	d_cache |= CPLB_L1_AOW | CPLB_WT;

#endif

#endif
@@ -91,9 +91,9 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) 
	/* Cover L2 memory */

#if L2_LENGTH > 0

	dcplb_tbl[cpu][i_d].addr = L2_START;

	dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;

	dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;

	icplb_tbl[cpu][i_i].addr = L2_START;

	icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;

	icplb_tbl[cpu][i_i++].data = L2_IMEMORY;

#endif



	first_mask_dcplb = i_d;