Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 41b55d23 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Olof Johansson:

 - A fix for OMAP5 and DRA7 to make the branch predictor hardening
   settings take proper effect on secondary cores

 - Disable USB OTG on am3517 since current driver isn't working

 - Fix thermal sensor register settings on Armada 38x

 - Fix suspend/resume IRQs on pxa3xx

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: am3517.dtsi:  Disable reference to OMAP3 OTG controller
  ARM: DRA7/OMAP5: Enable ACTLR[0] (Enable invalidates of BTB) for secondary cores
  ARM: pxa: irq: fix handling of ICMR registers in suspend/resume
  ARM: dts: armada-38x: use the new thermal binding
parents 37b5dca2 13e66cee

arch/arm/boot/dts/am3517.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -91,6 +91,11 @@ 
	};

};



/* Table Table 5-79 of the TRM shows 480ab000 is reserved */

&usb_otg_hs {

	status = "disabled";

};



&iva {

	status = "disabled";

};

arch/arm/boot/dts/armada-38x.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ 


			thermal: thermal@e8078 {

				compatible = "marvell,armada380-thermal";

				reg = <0xe4078 0x4>, <0xe4074 0x4>;

				reg = <0xe4078 0x4>, <0xe4070 0x8>;

				status = "okay";

			};

arch/arm/mach-omap2/omap-smp.c

+41 −0
Original line number Diff line number Diff line
@@ -109,6 +109,45 @@ void omap5_erratum_workaround_801819(void) 
static inline void omap5_erratum_workaround_801819(void) { }

#endif



#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

/*

 * Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with

 * ICIALLU) to activate the workaround for secondary Core.

 * NOTE: it is assumed that the primary core's configuration is done

 * by the boot loader (kernel will detect a misconfiguration and complain

 * if this is not done).

 *

 * In General Purpose(GP) devices, ACR bit settings can only be done

 * by ROM code in "secure world" using the smc call and there is no

 * option to update the "firmware" on such devices. This also works for

 * High security(HS) devices, as a backup option in case the

 * "update" is not done in the "security firmware".

 */

static void omap5_secondary_harden_predictor(void)

{

	u32 acr, acr_mask;



	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));



	/*

	 * ACTLR[0] (Enable invalidates of BTB with ICIALLU)

	 */

	acr_mask = BIT(0);



	/* Do we already have it done.. if yes, skip expensive smc */

	if ((acr & acr_mask) == acr_mask)

		return;



	acr |= acr_mask;

	omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);



	pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",

		 __func__, smp_processor_id());

}

#else

static inline void omap5_secondary_harden_predictor(void) { }

#endif



static void omap4_secondary_init(unsigned int cpu)

{

	/*
@@ -131,6 +170,8 @@ static void omap4_secondary_init(unsigned int cpu) 
		set_cntfreq();

		/* Configure ACR to disable streaming WA for 801819 */

		omap5_erratum_workaround_801819();

		/* Enable ACR to allow for ICUALLU workaround */

		omap5_secondary_harden_predictor();

	}



	/*

arch/arm/mach-pxa/irq.c

+2 −2
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ static int pxa_irq_suspend(void) 
{

	int i;



	for (i = 0; i < pxa_internal_irq_nr / 32; i++) {

	for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {

		void __iomem *base = irq_base(i);



		saved_icmr[i] = __raw_readl(base + ICMR);
@@ -204,7 +204,7 @@ static void pxa_irq_resume(void) 
{

	int i;



	for (i = 0; i < pxa_internal_irq_nr / 32; i++) {

	for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {

		void __iomem *base = irq_base(i);



		__raw_writel(saved_icmr[i], base + ICMR);