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Commit 41a524ab authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/kms: add dpm support for KB/KV 



This adds dpm support for KB/KV asics.  This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6bb5c0d7

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \

	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o



radeon-$(CONFIG_COMPAT) += radeon_ioc32.o

radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o

drivers/gpu/drm/radeon/cik.c

+27 −3
Original line number Diff line number Diff line
@@ -6593,6 +6593,7 @@ int cik_irq_set(struct radeon_device *rdev) 
	u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;

	u32 grbm_int_cntl = 0;

	u32 dma_cntl, dma_cntl1;

	u32 thermal_int;



	if (!rdev->irq.installed) {

		WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -6625,6 +6626,9 @@ int cik_irq_set(struct radeon_device *rdev) 
	cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;

	cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;



	thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &

		~(THERM_INTH_MASK | THERM_INTL_MASK);



	/* enable CP interrupts on all rings */

	if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {

		DRM_DEBUG("cik_irq_set: sw int gfx\n");
@@ -6782,6 +6786,11 @@ int cik_irq_set(struct radeon_device *rdev) 
		hpd6 |= DC_HPDx_INT_EN;

	}



	if (rdev->irq.dpm_thermal) {

		DRM_DEBUG("dpm thermal\n");

		thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;

	}



	WREG32(CP_INT_CNTL_RING0, cp_int_cntl);



	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
@@ -6816,6 +6825,8 @@ int cik_irq_set(struct radeon_device *rdev) 
	WREG32(DC_HPD5_INT_CONTROL, hpd5);

	WREG32(DC_HPD6_INT_CONTROL, hpd6);



	WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);



	return 0;

}
@@ -7027,6 +7038,7 @@ int cik_irq_process(struct radeon_device *rdev) 
	bool queue_hotplug = false;

	bool queue_reset = false;

	u32 addr, status, mc_client;

	bool queue_thermal = false;



	if (!rdev->ih.enabled || rdev->shutdown)

		return IRQ_NONE;
@@ -7377,6 +7389,19 @@ int cik_irq_process(struct radeon_device *rdev) 
				break;

			}

			break;

		case 230: /* thermal low to high */

			DRM_DEBUG("IH: thermal low to high\n");

			rdev->pm.dpm.thermal.high_to_low = false;

			queue_thermal = true;

			break;

		case 231: /* thermal high to low */

			DRM_DEBUG("IH: thermal high to low\n");

			rdev->pm.dpm.thermal.high_to_low = true;

			queue_thermal = true;

			break;

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");

			break;

		case 241: /* SDMA Privileged inst */

		case 247: /* SDMA Privileged inst */

			DRM_ERROR("Illegal instruction in SDMA command stream\n");
@@ -7416,9 +7441,6 @@ int cik_irq_process(struct radeon_device *rdev) 
				break;

			}

			break;

		case 233: /* GUI IDLE */

			DRM_DEBUG("IH: GUI idle\n");

			break;

		default:

			DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);

			break;
@@ -7432,6 +7454,8 @@ int cik_irq_process(struct radeon_device *rdev) 
		schedule_work(&rdev->hotplug_work);

	if (queue_reset)

		schedule_work(&rdev->reset_work);

	if (queue_thermal)

		schedule_work(&rdev->pm.dpm.thermal.work);

	rdev->ih.rptr = rptr;

	WREG32(IH_RB_RPTR, rdev->ih.rptr);

	atomic_set(&rdev->ih.lock, 0);

drivers/gpu/drm/radeon/cikd.h

+72 −0
Original line number Diff line number Diff line
@@ -28,10 +28,59 @@ 


#define CIK_RB_BITMAP_WIDTH_PER_SH  2



/* DIDT IND registers */

#define DIDT_SQ_CTRL0                                     0x0

#       define DIDT_CTRL_EN                               (1 << 0)

#define DIDT_DB_CTRL0                                     0x20

#define DIDT_TD_CTRL0                                     0x40

#define DIDT_TCP_CTRL0                                    0x60



/* SMC IND registers */

#define NB_DPM_CONFIG_1                                   0x3F9E8

#       define Dpm0PgNbPsLo(x)                            ((x) << 0)

#       define Dpm0PgNbPsLo_MASK                          0x000000ff

#       define Dpm0PgNbPsLo_SHIFT                         0

#       define Dpm0PgNbPsHi(x)                            ((x) << 8)

#       define Dpm0PgNbPsHi_MASK                          0x0000ff00

#       define Dpm0PgNbPsHi_SHIFT                         8

#       define DpmXNbPsLo(x)                              ((x) << 16)

#       define DpmXNbPsLo_MASK                            0x00ff0000

#       define DpmXNbPsLo_SHIFT                           16

#       define DpmXNbPsHi(x)                              ((x) << 24)

#       define DpmXNbPsHi_MASK                            0xff000000

#       define DpmXNbPsHi_SHIFT                           24



#define SMC_SYSCON_MSG_ARG_0                              0x80000068



#define GENERAL_PWRMGT                                    0xC0200000

#       define GLOBAL_PWRMGT_EN                           (1 << 0)

#       define GPU_COUNTER_CLK                            (1 << 15)



#define SCLK_PWRMGT_CNTL                                  0xC0200008

#       define RESET_BUSY_CNT                             (1 << 4)

#       define RESET_SCLK_CNT                             (1 << 5)

#       define DYNAMIC_PM_EN                              (1 << 21)



#define CG_FTV_0                                          0xC02001A8



#define LCAC_SX0_OVR_SEL                                  0xC0400D04

#define LCAC_SX0_OVR_VAL                                  0xC0400D08



#define LCAC_MC0_OVR_SEL                                  0xC0400D34

#define LCAC_MC0_OVR_VAL                                  0xC0400D38



#define LCAC_MC1_OVR_SEL                                  0xC0400D40

#define LCAC_MC1_OVR_VAL                                  0xC0400D44



#define LCAC_MC2_OVR_SEL                                  0xC0400D4C

#define LCAC_MC2_OVR_VAL                                  0xC0400D50



#define LCAC_MC3_OVR_SEL                                  0xC0400D58

#define LCAC_MC3_OVR_VAL                                  0xC0400D5C



#define LCAC_CPL_OVR_SEL                                  0xC0400D84

#define LCAC_CPL_OVR_VAL                                  0xC0400D88



#define	CG_MULT_THERMAL_STATUS				0xC0300014

#define		ASIC_MAX_TEMP(x)			((x) << 0)

#define		ASIC_MAX_TEMP_MASK			0x000001ff
@@ -60,6 +109,16 @@ 
#	define ZCLK_SEL(x)				((x) << 8)

#	define ZCLK_SEL_MASK				0xFF00



#define	CG_THERMAL_INT_CTRL				0xC2100028

#define		DIG_THERM_INTH(x)			((x) << 0)

#define		DIG_THERM_INTH_MASK			0x000000FF

#define		DIG_THERM_INTH_SHIFT			0

#define		DIG_THERM_INTL(x)			((x) << 8)

#define		DIG_THERM_INTL_MASK			0x0000FF00

#define		DIG_THERM_INTL_SHIFT			8

#define 	THERM_INTH_MASK				(1 << 24)

#define 	THERM_INTL_MASK				(1 << 25)



/* PCIE registers idx/data 0x38/0x3c */

#define PB0_PIF_PWRDOWN_0                                 0x1100012 /* PCIE */

#       define PLL_POWER_STATE_IN_TXS2_0(x)               ((x) << 7)
@@ -173,6 +232,19 @@ 
#define PCIE_INDEX  					0x38

#define PCIE_DATA  					0x3C



#define SMC_IND_INDEX_0  				0x200

#define SMC_IND_DATA_0  				0x204



#define SMC_IND_ACCESS_CNTL  				0x240

#define		AUTO_INCREMENT_IND_0			(1 << 0)



#define SMC_MESSAGE_0  					0x250

#define		SMC_MSG_MASK				0xffff

#define SMC_RESP_0  					0x254

#define		SMC_RESP_MASK				0xffff



#define SMC_MSG_ARG_0  					0x290



#define VGA_HDP_CONTROL  				0x328

#define		VGA_MEMORY_DISABLE				(1 << 4)