Loading arch/arm/include/asm/cacheflush.h +21 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,21 @@ * DMA Cache Coherency * =================== * * dma_inv_range(start, end) * * Invalidate (discard) the specified virtual address range. * May not write back any entries. If 'start' or 'end' * are not cache line aligned, those lines must be written * back. * - start - virtual start address * - end - virtual end address * * dma_clean_range(start, end) * * Clean (write back) the specified virtual address range. * - start - virtual start address * - end - virtual end address * * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. Loading @@ -115,6 +130,8 @@ struct cpu_cache_fns { void (*dma_map_area)(const void *, size_t, int); void (*dma_unmap_area)(const void *, size_t, int); void (*dma_inv_range)(const void *, const void *); void (*dma_clean_range)(const void *, const void *); void (*dma_flush_range)(const void *, const void *); } __no_randomize_layout; Loading @@ -140,6 +157,8 @@ extern struct cpu_cache_fns cpu_cache; * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ #define dmac_inv_range cpu_cache.dma_inv_range #define dmac_clean_range cpu_cache.dma_clean_range #define dmac_flush_range cpu_cache.dma_flush_range #else Loading @@ -159,6 +178,8 @@ extern void __cpuc_flush_dcache_area(void *, size_t); * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ extern void dmac_inv_range(const void *start, const void *end); extern void dmac_clean_range(const void *start, const void *end); extern void dmac_flush_range(const void *, const void *); #endif Loading arch/arm/include/asm/glue-cache.h +2 −0 Original line number Diff line number Diff line Loading @@ -159,6 +159,8 @@ static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) #define dmac_flush_range __glue(_CACHE,_dma_flush_range) #define dmac_inv_range __glue(_CACHE, _dma_inv_range) #define dmac_clean_range __glue(_CACHE, _dma_clean_range) #endif #endif arch/arm/mm/cache-v7.S +4 −2 Original line number Diff line number Diff line Loading @@ -350,7 +350,7 @@ ENDPROC(v7_flush_kern_dcache_area) * - start - virtual start address of region * - end - virtual end address of region */ v7_dma_inv_range: ENTRY(v7_dma_inv_range) dcache_line_size r2, r3 sub r3, r2, #1 tst r0, r3 Loading Loading @@ -380,7 +380,7 @@ ENDPROC(v7_dma_inv_range) * - start - virtual start address of region * - end - virtual end address of region */ v7_dma_clean_range: ENTRY(v7_dma_clean_range) dcache_line_size r2, r3 sub r3, r2, #1 bic r0, r0, r3 Loading Loading @@ -466,6 +466,8 @@ ENDPROC(v7_dma_unmap_area) globl_equ b15_dma_map_area, v7_dma_map_area globl_equ b15_dma_unmap_area, v7_dma_unmap_area globl_equ b15_dma_inv_range, v7_dma_inv_range globl_equ b15_dma_clean_range, v7_dma_clean_range globl_equ b15_dma_flush_range, v7_dma_flush_range define_cache_functions b15 arch/arm/mm/proc-macros.S +2 −0 Original line number Diff line number Diff line Loading @@ -335,6 +335,8 @@ ENTRY(\name\()_cache_fns) .long \name\()_flush_kern_dcache_area .long \name\()_dma_map_area .long \name\()_dma_unmap_area .long \name\()_dma_inv_range .long \name\()_dma_clean_range .long \name\()_dma_flush_range .size \name\()_cache_fns, . - \name\()_cache_fns .endm Loading arch/arm/mm/proc-syms.c +3 −0 Original line number Diff line number Diff line Loading @@ -30,6 +30,9 @@ EXPORT_SYMBOL(__cpuc_flush_user_all); EXPORT_SYMBOL(__cpuc_flush_user_range); EXPORT_SYMBOL(__cpuc_coherent_kern_range); EXPORT_SYMBOL(__cpuc_flush_dcache_area); EXPORT_SYMBOL(dmac_inv_range); EXPORT_SYMBOL(dmac_clean_range); EXPORT_SYMBOL(dmac_flush_range); #else EXPORT_SYMBOL(cpu_cache); #endif Loading Loading
arch/arm/include/asm/cacheflush.h +21 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,21 @@ * DMA Cache Coherency * =================== * * dma_inv_range(start, end) * * Invalidate (discard) the specified virtual address range. * May not write back any entries. If 'start' or 'end' * are not cache line aligned, those lines must be written * back. * - start - virtual start address * - end - virtual end address * * dma_clean_range(start, end) * * Clean (write back) the specified virtual address range. * - start - virtual start address * - end - virtual end address * * dma_flush_range(start, end) * * Clean and invalidate the specified virtual address range. Loading @@ -115,6 +130,8 @@ struct cpu_cache_fns { void (*dma_map_area)(const void *, size_t, int); void (*dma_unmap_area)(const void *, size_t, int); void (*dma_inv_range)(const void *, const void *); void (*dma_clean_range)(const void *, const void *); void (*dma_flush_range)(const void *, const void *); } __no_randomize_layout; Loading @@ -140,6 +157,8 @@ extern struct cpu_cache_fns cpu_cache; * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ #define dmac_inv_range cpu_cache.dma_inv_range #define dmac_clean_range cpu_cache.dma_clean_range #define dmac_flush_range cpu_cache.dma_flush_range #else Loading @@ -159,6 +178,8 @@ extern void __cpuc_flush_dcache_area(void *, size_t); * is visible to DMA, or data written by DMA to system memory is * visible to the CPU. */ extern void dmac_inv_range(const void *start, const void *end); extern void dmac_clean_range(const void *start, const void *end); extern void dmac_flush_range(const void *, const void *); #endif Loading
arch/arm/include/asm/glue-cache.h +2 −0 Original line number Diff line number Diff line Loading @@ -159,6 +159,8 @@ static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { } #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) #define dmac_flush_range __glue(_CACHE,_dma_flush_range) #define dmac_inv_range __glue(_CACHE, _dma_inv_range) #define dmac_clean_range __glue(_CACHE, _dma_clean_range) #endif #endif
arch/arm/mm/cache-v7.S +4 −2 Original line number Diff line number Diff line Loading @@ -350,7 +350,7 @@ ENDPROC(v7_flush_kern_dcache_area) * - start - virtual start address of region * - end - virtual end address of region */ v7_dma_inv_range: ENTRY(v7_dma_inv_range) dcache_line_size r2, r3 sub r3, r2, #1 tst r0, r3 Loading Loading @@ -380,7 +380,7 @@ ENDPROC(v7_dma_inv_range) * - start - virtual start address of region * - end - virtual end address of region */ v7_dma_clean_range: ENTRY(v7_dma_clean_range) dcache_line_size r2, r3 sub r3, r2, #1 bic r0, r0, r3 Loading Loading @@ -466,6 +466,8 @@ ENDPROC(v7_dma_unmap_area) globl_equ b15_dma_map_area, v7_dma_map_area globl_equ b15_dma_unmap_area, v7_dma_unmap_area globl_equ b15_dma_inv_range, v7_dma_inv_range globl_equ b15_dma_clean_range, v7_dma_clean_range globl_equ b15_dma_flush_range, v7_dma_flush_range define_cache_functions b15
arch/arm/mm/proc-macros.S +2 −0 Original line number Diff line number Diff line Loading @@ -335,6 +335,8 @@ ENTRY(\name\()_cache_fns) .long \name\()_flush_kern_dcache_area .long \name\()_dma_map_area .long \name\()_dma_unmap_area .long \name\()_dma_inv_range .long \name\()_dma_clean_range .long \name\()_dma_flush_range .size \name\()_cache_fns, . - \name\()_cache_fns .endm Loading
arch/arm/mm/proc-syms.c +3 −0 Original line number Diff line number Diff line Loading @@ -30,6 +30,9 @@ EXPORT_SYMBOL(__cpuc_flush_user_all); EXPORT_SYMBOL(__cpuc_flush_user_range); EXPORT_SYMBOL(__cpuc_coherent_kern_range); EXPORT_SYMBOL(__cpuc_flush_dcache_area); EXPORT_SYMBOL(dmac_inv_range); EXPORT_SYMBOL(dmac_clean_range); EXPORT_SYMBOL(dmac_flush_range); #else EXPORT_SYMBOL(cpu_cache); #endif Loading